Jeffrey Carano wrote:
>
> One of my customers asked if there is a formula to figure the needed
> width of a trace, given a specified copper weight, for the amount of
> power he wants to put through it.
> Second, what spacing does he need between these traces?
> Thank you in advance. Jeff
>
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 Hi Jeffrey--

The conductor current carrying capablity for various thermal rises above
ambient chart is contained in the IPC's design documents, such as
IPC-D-275 and the newer series of documents IPC-2221 for traditional
rigid printed boards.

A formula for generating the chart was recently presented at IPCWorks
'97 "Emperical equation for sizing copper PWB traces" by John McHardy
and Mehendra Gandhi, Hughes Aircraft, technical paper SO6-2-1, and is in
the form of I = k (T^0.44) (A^0.725)

        Where:
                I is current in amps.
                k is a constant = 0.048 for "external", and 0.024 for
                "internal" conductive patterns.

The electrical spacing between conductive pattrens is likewise located
in the previously mention IPC documents.  It would be in your best
interests (reliability of product) and not (or do some good long-term
testing) to use the design requirements for "high voltage" (> ~ 300 Vdc
or Vac peak) if you try to combine currently used digital-like design
practices and multilayer printed board technology in high voltage
sections.  If you're serious about long-term functional reliability, the
electrical stress (voltager gradient) SHALL be < 400 V/mm (10
V/millinch).

Ralph

--
Ralph Hersey

Ralph Hersey & Associates
3885 Mills Way
Livermore, CA 94550-3319
PHN: 510.454.9805
FAX: 510.454.9805
e-mail: [log in to unmask]

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