To all those who were unable to decode or read this message, I am re-sending
without the coupon design and un-encoded:


Circuit Reliability Testing

Concoat are able to assist in providing Process Characterisation/Validation
tests using new Auto-SIR(tm) Surface Insulation Resistance (SIR) test methods
with Frequent Monitoring, Trend Analysis (FMTA) techniques. (Sorry for the
advert but this is a unique capability.)

SIR testing measures the actual effects of both Ionic and Non-Ionic
contamination, on the surface insulation resistance of your representative
assembly under conditions of accelerated ageing, to better predict the
reliability of your product.

The testing should be conducted according to:

Either: J-STD-001B Class 2 (7 day test)
Or:     J-STD-001B Class 3 (7 day test cycling)

Both require special SIR test coupons incorporating inter-digitated comb
patterns that should be processed simultaneously with the existing production
processes.

These coupons, such as IPC-B36 should permit component overmounting to the
test patterns. I am not sure whether the following drawing will be readable
but here is another example of a suitable coupon. I can supply Gerber artwork
if required.

The test should offer a complete SIR overview of the total process. The
coupons must be prepared by production means and entered into the test at
subsequent stages of the production process.
For example, and based upon an original enquiry on the TechNet by Jim Mathis:

Stage 1 Bare FR4 as from supplier                                       4 coupons
Stage 2 Solder resist applied and cured                                 4 coupons
Stage 3 Application of SMT adhesive side 1                              4 coupons
Stage 4 Application of Paste, reflow                                    4 coupons
Stage 5 Application of flux and wave soldered                           4 coupons
Stage 6 Application of Paste, components mounted, reflow                4 coupons
Stage 7 Application of flux and components mountd, wave soldered        4 coupons

If applicable, then:

Stage 8 Boards are cleaned                                              4 coupons
Stage 9 Conformal Coating applied and cured                             4 coupons

Obviously, the manufacturing process and therefore the number of test coupons
involved, will vary from customer to customer. If only a fully assembled final
sample is tested, then any process problems cannot be so easily identified.

The testing that can now be provided:

* Very low test leakage current detection ( <10-12 A) providing far more
sensitive testing.
* Each test site is able to be monitored at 10 minute intervals. This gives
far greater opportunity to detect  Electro-Migration in the form of Dendrites.
* It permits CAF influences to be detected.
* Dendrites may be preserved to facilitate subsequent and separate failure
analysis.
* Varying test voltages may be used

We consider that, because of the low current test capability, reverse bias is
unnecessary as it does not properly reflect actual assembly operating
conditions.

From this testing, the synergistic effect of each process step can be seen in
the final evaluation. For example low SIR might come from a problem in the
bulk FR4 in Stage 1, or may be introduced by a contaminated cleaning tank in
Stage 8. Or low SIR could indicate an adverse and unpredictable reaction
between the solder resist and solder flux.

I am sure that test specialists such as: CSL, Trace, Robisan, in the USA; NPL
in the UK; IVF in Sweden etc., will be willing and able to conduct this work.

I would be grateful to hear peoples views on the above and how relevant they
feel it may be to their reliability issues.

Graham Naisbitt


Concoat Ltd                                     Email: [log in to unmask]
Alasan House, Albany Park                       Tel:    +44 (0)1276 691100
Camberley, Surrey GU15 2PL UK           Fax:    +44 (0)1276 691227

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