Hi Kalpesh,

Your best source of information on buried resistor (bare board) testing
is from the test equipment manufacturers. Standard test equipment,
either bed-of-nails or flying probe machines may be used. You will have
to buy a special software package.
In regards to netlists, IPC is coming out with the IPC-D-356A, Bare
Substrate Electrical Test Data Format. It remains to be seen if it will
be supported at the CAD/CAM level. For now, the answer to your questions
about buried resistor netlists is, "Yes you can extract a netlist from
the gerber files and yes you can also use a CAD generated netlist with a
secondary resistor file." Outside test services have custom programs to
dea with resistor networks. They generally prefer the gerber extraction,
particularily if they're building fixtures for innerlayer testing.
Unlike final bare board electrical test, innerlayer testing requires
fixtures that match the panel layout.

In regards to fault verification, the tester will output a XY list
showing the resistor location and ohmic values of the out-of-tolerance
rersistors. (The state of the art falls far short of the sophistication
of AOI systems).

This may be a case of "the tail wagging the dog," but the test guys seem
to be more responsive than the suppliers of the CAD layout tools and
software packages, so address your questions to them first.

Best Regards,  Dan Brandler, Ohmega Technologies, Inc. www.ohmega.com.

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