Steve,

Over the last few years of having the chance to do some RF board
layout, I get the impression that it is not being addressed at all. Its true,
the RF engineers don't like the thermal reliefs on SMT lands because it
hinders their circuits' performance. In my opinion, these same engineers
should think long and hard about the volume of business they are going
after with a given product. Perhaps the sensitivity of a given RF circuit
would dictate that the lands only be defined by the mask. However,
ideally,  high-volume assembly would be given a certain amount of
consideration by these people.
Yes- you touched a nerve.

John Swinehart
BFGoodrich Avionics Systems, Inc.

>>> Steve Collins writes:

We had a Capacitor manufacturer in our plant the other day and we
were
talking about design consideration of chip components. A statement that
it
was not necessary to use thermal reliefs to connect the SM component
pad to
a large ground plane (we design RF boards to 860 MHz soon to 1Gig).
That
the practice of using the soldermask to define the solderable area in
these
large ground planes was sufficient. This seems to go against the earlier
practices of requiring thermals to prevent thermal shock, tombstoning of
the parts & Rework considerations. We use both top side and bottom
side SMT
and sometimes on the same board. Our EE's love this idea but are we
asking
for trouble in reliability down the line

My question:

How are other people in the industry dealing with this issue?

Has anyone gone this rout and then returned to using thermals. If so can
you share your problems or findings.

Thanks again for everyone's help.

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