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August 1997

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Subject:
From:
"Shaub, John, E (PA62)" <[log in to unmask]>
Reply To:
TechNet Mail Forum.
Date:
Fri, 1 Aug 1997 13:00:30 -0400
Content-Type:
text/plain
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text/plain (59 lines)
Tom, in my most recent discussions with board vendors, the smallest I
can get away
with without special handling is .025 pad external, .027 pad internal,
.040 void for planes,
and .012 +/-.003 finished hole. Suggestions also include tear dropping,
to limit hole break-out.

I am interested in hearing what other designers are specifying as
minimums.

Regards,
John E. Shaub
Honeywell IAC Inc.



> ----------
> From:         Thomas Kropski[SMTP:[log in to unmask]]
> Sent:         Friday, August 01, 1997 12:06 PM
> To:   [log in to unmask]
> Subject:      Via hole/pad size
>
> As a PWB designer, one of my goals is not to design circuits which
> cause
> problems during fab or test.
>
> >From the fab persons,  what is the smallest reliable via hole/pad
> size
> combination acceptable in normal fabrication.  I would expect these
> boards would have to meet IPC Class 2 or 3 requirements.
>
> Appreciate your responses.
>
> Thanks in advance,
>
> Tom Kropski
> Sierra Technologies, Inc
>
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