We are using .015" for via and .035" for the pad.  Some of the vias do
not get filled with solder during wave.  The test point vias that do not get
filled are then filled by hand.  Is there a more optimum pad and via size to
get a good yield of filled vias without losing too much real-estate on the
board?  We do not have the resources, at present,  to pre-determine
which vias to use for test points during board design.
   Are there other options such having the board house fill the test vias,
or using the stencil to put solder paste on the test vias.  Does anyone
have  good results in this area??