Marti,
From how you describe the defect, its seems you have a larger problem
on your hands. You may want to elaborate on the type and degree of
defect (i.e., 1-2 per QFP, random throughout the assy, at the edges,
in the center, 1 QFP in particular, etc). Look at the following
variables:
1. Possible IMC (intermetallic compound) present on the SMT lands. It
sounds as if the solder is wetting properly to the lead and that
the land has some type of contaminate(s). Any thin and porous SnPb
may exhibit Cu5Sn6 crystal growth (oxidation). This will limit the
solderabilty. To what degree, I'm not sure. I have found this
problem in the past and have methods for correcting.
Sample PCB date codes, XRF measurements of SnPb lands, etc.
2. Some QFP packages will give you problems, depending how the package
is rotated on the PCB. Some leads may be heatsinked to a large
plane on the die, causing it not to solder.
3. One defect that I am having difficulties identifying is lead
coplanarity. Is the lead being damaged at the supplier,
distributer, kitting or on the line? I don't know and have put off
investigating. Any suggestions on this topic would be helpful.
I beleive the problem lies with item 1 and that 2/3 are other minor
variables.
With regards to design, remember that IPC-SM-782 is a design standard
for which to begin your designs and does not apply to everyone's
product. I am not sure how your CAD/CAM group approached the layout
of the PCB, but here's a suggestion. SMT Plus and the like, are great
design books but found land layouts did not always match the
manufacturers suggested QFP patterns which led to assembly P&P
problems. I had our design group transition the whole library to
IPC-SM-782 with following suggestion.
w=width, p=pitch, l=land
W=P/2
L=W*5
i.e., W=.012/2
W=.006
L=.006*5
L=.030
LAND= .006x.030
I'm not sure where I got this basic formula, but have been using it
for many years. It was recently used on our PCMCIA design with 450
components in a 5.2inē area with great success.
With regards to solderpaste volume, the above will help some, however
the thickness of your stencil is big contributer. Are you using Laser
or Chem etch stencils? Are the stencils chemical polished? What is
you soldermask thickness with respect to stencil thickness? Is the
stencil to pad thickness ratio correct? There are many variables that
need addressing here. I can help you more of line if needed.
Look for the following for bridging. Make sure your using the right
solderpaste particle size, viscosity. minimize slump (temp/RH),
John Gulley
1255 W. 15th St.
Plano, TX 75075
972.578.3928
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Subject: [TECHNET] Assy & Design SMT
Author: "Tully; Marti (AZ15)" <[log in to unmask]> at Internet
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