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Date: | Thu, 10 Jul 1997 08:22:32 -0700 |
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Mark --
I was interested to note that you say your solder DPM is very consistent from
product to product. Assuming you're talking about the DPM directly out of wave
solder or reflow solder, before any touch-up is done....then this is definitely
NOT the case with us. Although consistent within a product, our defect rates can
easily vary by a factor of 10 from product to product...in fact, there is more
like a factor of 100 difference in DPM between our best and worst
product...illustrating the paramount importance of design for manufacturability!
-- V. Chapman
On Thu, 10 Jul 1997 04:22:11 -0700 Mark W. Spitnale wrote:
> From: Mark W. Spitnale <[log in to unmask]>
> Date: Thu, 10 Jul 1997 04:22:11 -0700
> Subject: Re: PPM Defect Counting
> To: [log in to unmask]
> Cc: [log in to unmask]
>
> FYI
> We count defects very similar to the way Rick has mentioned with the
> exception that if a solder short has affected more than 2 leads the no. of
> shorts is Leads affected minus 1 with in a grouping. I think this scenrio
> more closely corelates to the way the opportunities were determined (i.e. no
> of lead that are potential for a short).
>
> P.S. The assembly oportunities should also include 1 for the board and 1
> for each stamp, label but these are insignificant numbers compared to often
> 2000 - 3000 solder and placement oppertunities per board. We also track our
> solder defects against just the solder opportunities and the
> placement/assembly defects against those opportunities to see how different
> products compare. As can be imagined solder DPM is very consistant amoungst
> most products. Placememnt defects however very, based off the density,
> package lead counts and # of oddball components.
>
>
> Mark Spitnale,
> Hughes Defense
> [log in to unmask]
>
> Resent-Sender: [log in to unmask]
> >>
> >>We count our defect opportunities as follows: one per component plus
> >>one per solder joint. A resistor would be three defect opportunities, a 144
> >>pin QFP would be 145 defect opportunities.
> >>
> >>We count actual defects as follows: Tombstone part is one defect.
> >>Insufficient solder on one pad is one defect. Solder short between three
> >>legs of an SOIC is one defect. Skewed SOIC is one defect.
> >>
> >>I have concerns that we are presenting an artificially low PPM rate by
> >>counting defects this way. Others have concern that if we count defects
> >>the same way we create opportunities, the PPM numbers will be inflated.
> >>
> >>I'm looking for info on how others in the industry count actual defects that
> >>affect more than one opportunity.
> >>
> >>Thanks. Rick Vernon, QA Manager [log in to unmask]
> >>
> >>***************************************************************************
> >>*
> >>
> >>
> >-
> >
> >
> ----------------------------------
> Mark W. Spitnale Phone: (219) 429-5992 Fax: (219) 429-
> Hughes Defense Communications Mail Stop: 25-31
> 1010 Production Road, Fort Wayne, IN 46808-4106
> Email: [log in to unmask]
>
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