We count our defect opportunities as follows: one per component plus
one per solder joint. A resistor would be three defect opportunities, a 144
pin QFP would be 145 defect opportunities.

We count actual defects as follows: Tombstone part is one defect.
Insufficient solder on one pad is one defect. Solder short between three
legs of an SOIC is one defect. Skewed SOIC is one defect.

I have concerns that we are presenting an artificially low PPM rate by
counting defects this way. Others have concern that if we count defects
the same way we create opportunities, the PPM numbers will be inflated.

I'm looking for info on how others in the industry count actual defects that
affect more than one opportunity.

Thanks.  Rick Vernon, QA Manager   [log in to unmask]

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