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July 1997

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Subject:
Via hole/pad size
From:
Thomas Kropski <[log in to unmask]>
Reply To:
[log in to unmask]
Date:
Fri, 01 Aug 1997 09:06:54 -0700
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As a PWB designer, one of my goals is not to design circuits which cause
problems during fab or test.

>From the fab persons,  what is the smallest reliable via hole/pad size
combination acceptable in normal fabrication.  I would expect these
boards would have to meet IPC Class 2 or 3 requirements.

Appreciate your responses.

Thanks in advance,

Tom Kropski
Sierra Technologies, Inc

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