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Date: | Wed, 30 Jul 1997 07:53:36 -0400 |
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George;
Actually not too hard. Extending dwell in developer may help. Rinse Spray
pressures are another obvious spot to play. Type of LPI will probably also have
an affect. We have no trouble with residual soldermask until very high aspect
ratios (greater than 10:1-12:1) or smaller than 8 mil holes. We continue to
try to push that envelope too.
The 2 mils finished hole tolerance isn't too bad with Immersion Au or with an
OSP on Copper.
Overall, your board probably won't be buildable in the far east, but it doesn't
sound too bad. We build similar all the time, and there are several other
shops with similar abilities.
Jim Herard
KBL, Product Quality Engineering
IBM Microelectronics Endicott
t/l 857-7026
---------------------- Forwarded by Jim Herard/Endicott/IBM on 07/30/97 07:42 AM
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07/29/97 09:14 AM
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Subject: Fab: soldermask capability
Hello Colleagues
One of my favorite 'smaller-is-better' design Engineers found a Nanionics
connector which uses 30 AGW wire for thru-hole leads, and recommends a thru
hole diameter of 12-16 mils. (Tight tolerance, too, huh?)
Question: Has anyone had problems with soldermask being left in these small
holes. The alleged failure mode is from the LPI-developer not able to
develop out soldermask in these holes, due their small diameter. This is
reasonable, since LPI developing likes alot of impingement.
I am looking for individuals who can commiserate, and who may have worked
out an alternative.
Other topic we could also talk about is holding a +/- .002 hole size with
solder coating; HASL?; Plate and reflow?; Ni/ Immersion Gold?
Finally, who in the Board industry told Nanionics this was an 'easy' thing
to do? (just kidding)
George Franck
Raytheon E-Systems
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