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The term "dentritic growth" is becoming more synonymous with 85 C /85
RH electrical testing. Some refer to it as "hydrolytic stability" as
well. This results in basically "shorts" in systems with tight
spacings and high voltages. The limiting factors really become the
substrate and covercoat types, as the minimum spacing at 100 volts to
be acceptable will depend on which combinations of materials are used.
Not all materials are equivalent!!! See recent proceedings from May
'96 IPC meeting in Phoenix.
______________________________ Reply Separator
_________________________________
Subject: DES: Track spacing for 100V on internal layers -Reply
Author: "Dennis Ostendorf" <[log in to unmask]> at -FABRIK/Internet
Date: 6/2/97 8:50 AM
From: Dennis Ostendorf
Date: Mon, Jun 2, 1997 8:50 AM
Subject: DES: Track spacing for 100V on internal layers -Reply
To: Duane B. Mahnke; TechNet
Cc: Gary_Willard-G10982
Gary,
You should not have a problem with .015 inch spacing for 100V (unless
you have contaminant(s) between the traces). In fact, I believe the
spacing is conservative & could be reduced.
Dennis Ostendorf
aaeee2o @snds.com
>>> Gary Willard-G10982
<[log in to unmask]> 06/02/97
06:15am >>>
Hello All
I am in need of some input on a design issue relating to track
spacing for 100V operation for the internal layers of a 4-layer
PCB.
This PCB is 2.0mm thick with a 1mm core and 35um copper. This
design has to withstand 85% humidity / 85deg temperature testing
for 500 Hours some of which is under 'power-up' conditions.
The current design has an epoxy based solder mask and conformal
coating and has an internal spacing of .015", which I believe
should be adequate as IPC-D-275 suggests a spacing of only
.004-.008" for class 3 assemblies, this figure of .015" has been
put to question so I am seeking further input.
my questions are:-
1) What does class 3 mean in terms of general environmental testing
and in particular 85/85 testing.
2) Does any body have practical knowledge of what a 'better
spacing'
may be.
Any input would be most appreciated.
Regards Gary Willard - Substrate Design Engineer
Motorola (UK)
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Subject: DES: Track spacing for 100V on internal layers -Reply
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