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43:15 1997 |
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| From [log in to unmask] Mon Jun 2 11: |
16:04 1997 |
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id m0wYZFt-000BjJC; Mon, 2 Jun 97 10:42 CDT |
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Gary,
You should not have a problem with .015 inch spacing for 100V (unless
you have contaminant(s) between the traces). In fact, I believe the
spacing is conservative & could be reduced.
Dennis Ostendorf
aaeee2o @snds.com
>>> Gary Willard-G10982
<[log in to unmask]> 06/02/97
06:15am >>>
Hello All
I am in need of some input on a design issue relating to track
spacing for 100V operation for the internal layers of a 4-layer
PCB.
This PCB is 2.0mm thick with a 1mm core and 35um copper. This
design has to withstand 85% humidity / 85deg temperature testing
for 500 Hours some of which is under 'power-up' conditions.
The current design has an epoxy based solder mask and conformal
coating and has an internal spacing of .015", which I believe
should be adequate as IPC-D-275 suggests a spacing of only
.004-.008" for class 3 assemblies, this figure of .015" has been
put to question so I am seeking further input.
my questions are:-
1) What does class 3 mean in terms of general environmental testing
and in particular 85/85 testing.
2) Does any body have practical knowledge of what a 'better
spacing'
may be.
Any input would be most appreciated.
Regards Gary Willard - Substrate Design Engineer
Motorola (UK)
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