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May 1997

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Subject:
From:
Jeff Seeger <[log in to unmask]>
Date:
Thu, 29 May 1997 18:24:38 -0400
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[log in to unmask] wrote:
> 
> 
>Has anyone had any experience with placing 0.035 pads (primary or
>secondary side of the PWB) on high-speed/fast-rise-time (sub ns) nets?
>
	We customarily replace standard vias with test vias to keep
	from introducing this problem.
 
>Did signal integrity go to pot?  Any design solutions as work-arounds?
> 
	The practice of adding a "stringer" to a stand-alone test
	pad is really just another stub, which depends entirely on
	your particular rules for stubs.

	If you are adding the test pad to a surface trace in-line,
	you're probably safe up an RF domain.

	Our method has been to prioritize, by signal sensitivity,
	the order of preference between testpointed through-vias,
	short stubs to test pads, and longer stubs to test pads.

	Also, if a short stub is needed on a delicate signal, the
	best bet is to make sure it is coming from a pin-escape
	and not a routing via.  This makes sure that any im-
	pact of the testpoint is at least in the shadow of the
	discontinuity from the package to the board.

	We've not seen ICT prepared in this fashion inject any
	signal integrity issues, however we've not tried using
	ICT on any Ghz-level analog circuits for the same reason
	you're expression caution.

	Good luck,
-- 
 
      Jeff Seeger                             Applied CAD Knowledge Inc
      Chief Technical Officer                      Tyngsboro, MA  01879
      [log in to unmask]                               508 649 9800

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