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May 1997

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Subject:
From:
Jeff Seeger <[log in to unmask]>
Date:
Sun, 18 May 1997 14:10:22 -0400
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dkorf wrote:
> 
	... snip ...
>      I'd love to compare notes with you sometime on this. I think we need
>      to address this as an industry. I have been working with the CAD
>      software suppliers to raise their awareness of what a test point is.
>      It turns out, they don't really have a clue.
> 	... snip ...

	Dana,

	I very much agree about the whole-industry perspective, as well as
	the CAD supplier angle.  The problem actually goes deeper than
	just the test perspective, all the way back to EDRC.  Most systems
	cannot easily identify the endpoints you seek, at least partially
	due to the same obstacle designers are in need of controlling: the
	overall topology of a net.

	To handle high-speed digital interconnect properly, we must know
	and verify the allowable end-points of a net (sources, stubs, and
	terminations).  I believe these are one and the same as the test
	points you seek.

	We can vouch for how difficult this is to determine without carry-
	ing and analyzing the full pin-use descriptions.  In porting route
	data between two CAD platforms that use entirely different models
	to describe etch topology, we found it quite difficult to ascertain
	and translate the intent with 100% accuracy.  This is especially
	true when either the target or the source do not have an inherent
	basis for determining what is the "proper" topology.  This sounds
	to me like the missing link in creating a good test file, no?

	My personal belief is that we won't have a satisfactory answer to
	this until CAD systems start recognizing a higher level of element
	type than "pin", "via" and "line".  That may be a long time coming.

	Meanwhile, best to all!
-- 
 
      Jeff Seeger                             Applied CAD Knowledge Inc
      Chief Technical Officer                      Tyngsboro, MA  01879
      [log in to unmask]                               508 649 9800

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