At 11:01 22/04/97 -0700, you wrote:
>I am designing a highspeed processor board and have come to the amazing
>requirement of having a VERY precise delay of 4.8 +/- .25 nanoseconds.
>
>Is this achievable in volume production printed circuit boards? 
>I am using FR4 medium and have 8 layers to work with. What geometries 
>and layering are best?
>
>My alternatives a custom/graded silicon delay lines or, perish the thought,
>an adjustment pot. Please help!!
>
>Ray Klein 
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Ray,

Should not be a problem.

Electrical signal speed in air dielectric is speed of light.
(approx one foot per nanosecond) [11.80285268" / ns]

Electrical signal speed in other dielectrics is inversely proportional to
the square root of the relative permitivity of the material (Er).  FR-4
has a relative permitivity of about 4.0 at higher frequencies, but 4.7 is
usually quoted by laminate suppliers at a test frequency of 1 MHz.

This leads to a propagation velocity on a internal trace of around half
the speed of light.  [ c / SQRT(4.0) ]
(approx 6 inches per nanosecond)

Therefore 4.8 ns +/- 0.25 ns translates to an internal stripline trace
length of 4.8 x 6 = 28.8" +/- 1.5" (a long trace!!)

Figures in inches using an exact conversion of speed of light in inches/ns
and assuming Er=4.0 gives: 28.32" +/- 1.47"

Er may be a little higher depending on glass to resin ratio in the actual
FR-4 so if we assume Er=4.2 (Vp = 5.76"/ns) this gives: 27.64" +/- 1.44"

I'm sure that you can control trace length to within +/- 1" so this should
be OK.  The only thing that could upset your "apple cart" is the added
capacitance of the via hole connections at each end of your delay line, this
will tend to slow the signal down by a few pico seconds.  You can approximate
this by assuming tr = 2.2*CR (where C=via hole capacitance, R=resistance,
CR is the time constant and 2.2*CR is the approximate rise time in seconds).

Assume R is matched to Zo (50 ohms) and a typical via will add a little
under 1 picofarad of capacitance, say 1pF to be on the safe side.

Then tr = 2.2 * 50 * 1*EXP(-12) = 110ps, but we have a connection via at
each end, so approximate total delay due to vias is around 0.22 ns!

This is not meant to be a rigourously derived solution, but I hope it has
presented the principles in a relatively simple format. 

ps Surface traces (microstrips, embedded microstrips & coated microstrips)
have part of the signal electromagnetic field propagating in AIR (not FR-4)
so the propagation velocity will tend to be a little faster for signals on
these controlled impedance trace structures.

Hope the above is helpful.

Best regards

Andy Burkhardt <[log in to unmask]>
Tel: + 44 1481 53081
Fax: + 44 1481 52476
http://www.polar.co.uk
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