I am looking for some insight into a design which requires controlled 
impedance.  We have been provided with the following design:

Proposed Build                                     Customer Spec

Layer 1 Signal  (1/2oz Cu)                Layer 1 Signal  (1/2oz Cu)
13mil prepreg                                  7mil prepreg min.
Layer 2 Plane (1oz Cu)                    Layer 2 Plane (1oz Cu)
8mil core                                           5mil core min.
Layer 3 Signal (1oz Cu)                   Layer 3 Signal (1oz Cu)
16mil prepreg                                  No spec on prepreg
Layer 4 Signal (1oz Cu)                   Layer 4 Signal (1oz Cu) 
8mil core                                          5mil core min.  
Layer 5 Plane (1oz Cu)                   Layer 5 Plane (1oz Cu)
13mil prepreg                                  7mil prepreg min.
Layer 6 Signal (1/2oz Cu)               Layer 6 Signal (1/2oz Cu)

Using the following variables, they are looking for the following 
impedance values:

Er = 4.84
T = 1.4mil (trace thickness)
H = 13mil (distance above plane)

Layer 1 with Ref Plane 2, 75ohm with 8mil conductor
Layer 4 with Ref Plane 5, 75ohm with 10mil conductor

After all that, this is my question, 

1. They appear to be treating the Layer 4/5 combination as an 
Embedded Microstrip.  Is this a valid assumption, or will the trace 
act more like an Offset Stripline between Layer 2 and Layer 5?

I would appreciate any feedback, both on or off-line on this 
subject.

Regards


John Parsons
Pre-Production Engineering Manager/Sales Engineer
Circuit Graphics Ltd.
8070 Winston St.
Burnaby, BC., Canada, V5A 2H5
Phone: (604) 420-3313 Fax: (604) 420-7525

Visit us on the Web: www.cirgraph.com

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