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Date: | Wed, 23 Apr 1997 08:45:45 -0400 |
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I am trying to specify the stackup for a controlled impedance
psudo-VME backplane. This backplane has controlled impedance traces of
100 Ohms and 50 Ohms. The current finished board thickness is 0.093"
and consists of ten layers, 4 of which are controlled impedance
layers.
In discussion with a local fab shop I am finding that in order to
create 100 Ohm traces, the width of the dielectric (for FR-4) is
prohibitive.
The only alternatives are to cut back on the number of layers or
substantially increase the PWB thickness (which causes a large
headache in finding components with sufficient lead length).
I have two questions concerning this and I hope someone out there can
help:
a.) Are there any major drawbacks to producing a backplane with, say,
4 layers only? i.e. Is there a limitation on the minimum number of
layers for a backplane PWB that I don't know about?
b.) How are standard 0.093" OTS VME backplanes produced? They seem to
me to have a fair number of layers without resorting to thick PWBs or
superfine traces.
I hope that someone out there has had experience with this kind of PWB
and can help me.
Thanks in advance,
--
Max.P.Harris
Hardware Design Engineer
Lockheed Martin Canada, Inc.
'Nil illegitime carborundum'
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