TECHNET Archives

April 1997

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Condense Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
X400-Content-Type:
P2-1988 ( 22 )
Old-Return-Path:
Date:
02 Apr 1997 17:29:57 -0600
From [log in to unmask] Thu Apr 3 08:
54:24 1997
Resent-From:
Conversion:
Allowed
Disclose-Recipients:
Prohibited
Resent-Sender:
TechNet-request [log in to unmask]
X-Status:
Status:
O
Priority:
normal
Precedence:
list
X-Loop:
Content-Return:
Allowed
X400-MTS-Identifier:
[/c=US/admd=MCI/prmd=Honeywell/; 05F4A3342EBF508D-HW-MTA-AZ]
TO:
"[log in to unmask]" <[log in to unmask]> (Return requested)
X-Mailing-List:
<[log in to unmask]> archive/latest/11657
Return-Path:
<TechNet-request>
Message-Id:
<05F4A3342EBF508D*/c=US/admd=MCI/prmd=Honeywell/o=AZ-MTA/ou=MSMail/ou=IAC/s=Tully/g=Marti/@MHS>
X400-Recipients:
non-disclosure;
X400-Originator:
Received:
by ipc.org (Smail3.1.28.1 #2) id m0wCZKE-000BilC; Wed, 2 Apr 97 17:20 CST
Resent-Message-ID:
<"iY0uS2.0.-fH.nckGp"@ipc>
Subject:
From:
"Tully, Marti (AZ15)" <[log in to unmask]>
Alternate-Recipient:
Allowed
X400-Received:
by mta HW-MTA-AZ in /c=US/admd=MCI/prmd=Honeywell/; converted ( IA5-Text); Relayed; 02 Apr 1997 17:29:57 -0600 by /c=US/admd=MCI/prmd=Honeywell/; converted ( IA5-Text); Relayed; 02 Apr 1997 17:29:57 -0600
Original-Encoded-Information-Types:
IA5-Text
Content-Identifier:
05F4A3342EBF508D
Parts/Attachments:
text/plain (27 lines)
Several of our PWB suppliers have used a via hole plugging process with the 
following sequence:  LPI, HASL, partially plug via hole (component side). 
   With mixed technology boards, our assemblers (in house, contracted etc.) 
all experience a phenomenon where the solder erupts from the top of the via 
during the wave process.  The eruption looks like a volcano and varies in 
severity.  This eruption  results in several problems including solderballs. 
  Most of the plugged vias lie under components and the spacing between vias 
can be equal to or <8mils.  Many components sit very close to the board's 
surface.

This seems the  PWB industry preferred method to plug holes when LPI is 
used.    How do assemblers prevent the eruption of the solder through the 
top of the plugged via during wave?  Is this a common problem in assembly 
 or rare?  

***************************************************************************
* TechNet mail list is provided as a service by IPC using SmartList v3.05 *
***************************************************************************
* To subscribe/unsubscribe send a message <to: [log in to unmask]>   *
* with <subject: subscribe/unsubscribe> and no text in the body.          *
***************************************************************************
* If you are having a problem with the IPC TechNet forum please contact   *
* Dmitriy Sklyar at 847-509-9700 ext. 311 or email at [log in to unmask]      *
***************************************************************************



ATOM RSS1 RSS2