Technetters,
Can anyone shed some light or lead me to another source on how to go
about designing in "testability" for an assembled circuit board? We have
densely packed boards with very little room left for traditional test
points (due to market driven forces). I have heard of J-tag and boundary
scan but are there any other new technologies out there that can provide
near 100% accessibility to all nodes? How are others of you out there in
Technet land dealing with this issue? Volume is very high as well so
an efficient testing methodology with troubleshooting capabilities is
needed. If anyone can provide assistance in this area, it would be
greatly appreciated.
David
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