I appreciate the interesting and suggestion on my project by David
Hoover,Paul Gould and Bob Holmes PhD and I hope for new opinion exchange.
Really the system can correct the outer-layer/solder files ,and the
upper/middle jig drill files(for fine pitch smd): but I think the problem
can be real if the global correction(resulting by the average of all the
layers) at limits of the board goes over +/-4 mils(*) that can be the result
of an improbable uniform behavior of all the layers(more complex lay-ups
mean smaller average-result correction). I think(but someone can tell I'm
not right!) 5 mils cannot create a mechanical mount problem but can craete a
problem in SMT automatic placement(I hope in suggestion of people with
experience in this field).
But a solution actually under simulation-test is putting intelligent
controls in 
image-processing(Gerber) software,that can discriminate SMT patterns from
hole-pads in outer layers: in this case the local offset is applied only on
hole-pads but not on smt(saving connections integrity).This can solve
solder,electrical test and smt-automatic-mounting, being unvaried the global
SMT image of the board(I think an offset correction is normally applied on
smt-automatic-mounting) ,naturally in not-abnormal shrinkage condition.     
Thanks for any answer,

(*) in a typical  25 mils pad with a 15 mils hole, a 4 mils offset results in a
    1 mil annular-ring on external layer that's better than an annular ring
    loss in some inner-layers.But i know italian and european rule-project
    limits and I would like to know more about U.S.A (in real normal
production           project).
        

                                                 Luca Marchese
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