While I do not disagree with respect to the reliability of inner layer hole
breakout on the INTENDED electrical connection, I would like to reiterate a
concern that I have previously posted on this topic. Specifically; the risk
of dielectric spacing violation between the hole exhibiting breakout and the
inevitable adjascent circuit, which, by the way, tends to be at the minimum
dielectric spacing by design. If printed circuit board specifications allow
breakout, the DESIGNERS MUST ensure that the spacing allowance on circuits
adjascent to inner layer pads, include this dielectric infringement. 

It seems unlikely that the design community would want to hear that the
spacing of circuitry has to be INCREASED at this time of diminishing dimensions.

Question : Have the IPC design rules taken into consideration this breakout
and it's potential effect on reduced dielectric spacing violations? 

Dave Rooke
Circo Craft - Pointe Claire

- - - - - - -

>     My vote is with Bob. Allow break-out. But I also feel that the
>actual PCB requirements should be considered.
>For the majority of what I see, break-out should provide adequate
>reliable innerconnects. Some things that I would
>not consider break-out allowed on would be large long backplanes that
>have long trace runs. Something that would
>continuously run hot. The TCE of resin and copper are different. If a
>PCB had break-in (break-out towards a trace
><without teardropping>), that might cause an intermittent open (thermal
>open). Such a product would be like a burn in board. (BIB)   I'm curious
>if the ITRI test vehicle had a sample that represented a large board.
>Also, were some of the
>variables tested various copper foil thicknesses and classes (like HTE
><4 and 6% elongation>) and various materials.
>
>Just Curious.
--- EOF ---

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