I've worked more designs than I can recall that use direct connect for
microvias (i.e. small vias that aren't used for through hole pins).
Literally millions of boards were built using these designs with no
problems that I'm aware of. I think a lot of companies have been
doing this for years.
I'm not sure if design parameters might have any affect on this. The
type of designs involved were 4 to 10 layer boards,.062" thick, with
finished holes sizes in range of 8 to 18 mil diameter.
Direct connect is particularly useful on high density areas of the
board and prevent the ground/power planes thermals from overlapping.
We use a small reference pad as Steve suggests.
Thad McMillan
______________________________ Reply Separator _________________________________
Subject: Re: DES: VIAS - Thermal vs. Direct
Author: [log in to unmask] at dell_unix
Date: 9/24/96 12:57 AM
We have just begun to use direct connect. We have built about 50 boards at
this point. We have yet to find any problems with the process. Your
question about reducing thermals: I would strongly recommend putting a
small thermal in your data. I gives you something to see as the data is
reviewed by everyone.
Steve Quinn
At 09:57 AM 9/24/96 -0700, you wrote:
>I was thrilled when the subject of thermal vias vs. direct-connect vias came
>up, because we were just discussing whether we should "go direct" last week.
>After reading all the responses... well, I'm just a little worried about it.
>Rather than quote everybody, here is a summary of what my boss will read if
>I show him this discussion:
>
>Two people, K.Barret and [log in to unmask], have used direct connections
>extensively, in all environments, all sizes, varied layer count, no
>problems. (and one ships about a million boards per year to prove it)
>
>B.Luthor concerned about heat transfer to plane, one reply stated trace from
>SMT pad to via was a thermal in itself. (I would tend to agree on that one)
>
>One side discussion about a PINK RING problem, without enough explanation to
>learn how pink ring would affect a board or how it is related to direct vias.
>
>Another side discussion about clearance vs. fab allowance, and another about
>reduced clearance (anti-pad) sizes. Won't affect our decision.
>
>A warning from Norm about CTE mismatch and the danger of board damage if
>direct connections are used.
>
>One reminder from G.Ferrari about the value of formal test procedures and a
>warning that what works for one design may not be appropriate for others.
>
>-=x=-
>
>Thanks to all who participated, this thread came along at the PERFECT time.
>Our board vendors don't care WHAT we do, so it is up to us. But before I go
>show this to others and we make the decision, are there any other issues
>that got left out? any elaboration necessary? any final comments?
>
>NOW THAT I THINK ABOUT IT, ALL OF THE REAL-WORLD RESPONSES WERE FAIRLY
>POSITIVE, AND ALL OF THE NEGATIVE RESPONSES WERE KIND OF THEORETICAL..!
>Am I misinterpreting? Are there any REAL horror stories out there?
>
>Also, if we remove the thermal apertures from our pwr/gnd via padstacks,
>should we replace them with a small aperture to "show" something there, or
>just leave it empty? Seems like it would be hard to track down connections
>looking at "direct-connected" film, any problems there?
>
>thanks in advance, (and Sorry to those who were tired of this subject)
>
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