All the theoretical reason for doing or not doing are fine and dandy,
and I respect Mr. Einarson very much, but the proof is in the pudding.
If people are tieing visa directly to the plance and have not had
problems, and indeed have increased the performance of their design,
then we MUST take another look at why we do things. I believe that
many of the things we do, and many of the rules of thumb we follow are
legacy items - there may have been a good reason at one time, but
technology has made the "reason" obsolete. This does not mean that I
do or do not advocate this particular item (I have asked the editors
of PC Fabrication and Circuits Assembly to comment on this via issue),
but that if there is something that seems to work, we should look at
it and ask questions.
I will be glad to put this particular issue on the schedule for one of
PCD's projects in early '97, ie. have several shops build a board with
via tied straignt to the gnd or pwr plane, run it over a wave etc. and
see what happens. As Lee Ritchey says "don't believe it just because
someone says so, ask for physicl proof.)
Pete Waddell
______________________________ Reply Separator _________________________________
Subject: Re: Design (vias/thermals)
Author: [log in to unmask] at Internet
Date: 9/18/96 7:52 AM
Tom Kavendek,
According to Norman S. Einarson (author of "Bare Board PWB Design Manual")
the only time you should tie any hole directly to a plane would be for
thermal reasons where there are multiple tie points (connections). The
reason is that there is thermal expansion and contractions with the bare
board processing, during board assembly and during normal product
operations. This thermal thing puts stress on the connection points where
they are tied to the plane and if they are tied directly to the plane then
the more chance of resistance to movement thus more chance for breaking
away. When the connection points are tied to the plane with thermals there
is less material thus less stress to the connection points allowing it to
move and less chance for breakage.
Please respond.
Greg Kaskey
Checkmate Electronics, Inc.
770.594.6000 x228
[log in to unmask]
----------
From: [log in to unmask]
To: [log in to unmask]; [log in to unmask]; Kaskey Greg
Subject: Re: Design (fwd)
Date: Tuesday, September 17, 1996 9:00AM
<<File Attachment: ENVELOPE.TXT>>
This discussion brings up another point....
Does it make sense to use thermal connections on vias?
Thermals were originally used on thru hole comps to increase
solderability of the leads, but now that is not necessary for SMT.
Is there any reason to use them for vias?
I've been using direct connection to the inner planes.
Tom Kavendek
Lucent Technologies
Murray Hill, N.J.
[log in to unmask]
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