Hi Max,

We have found, particularily when using an autorouter, that the ground
and power planes get really punched full of holes.  These holes are the
anti pads, and far and away the greatest offenders are the anti pads
caused by vias.  It is possible that the via anti pads, if left unchecked,
form a barrier, or a moat, in the plane.  In some cases I have seen ground
and power islands, areas of isolation, formed by excessive anti pads. 
These barriers screw up (a technical term...) the signal return path, 
hence hindering signal quality.  In addition, our emi/signal quality 
engineers have complained about traces passing over areas of the board
where there is no reference plane.  As I referred to earlier, they call
the effect on signal quality "impedance bumps".  While the effect of passing
over one anti pad (an area of no reference plane) might well be slight,
the cumulative effect of passing by a large number of areas such as this
can be significant.

These conditions can be improved by increasing the via to via spacing 
constraint, however this will hinder the autorouter, creating more unroutes 
on the board.  If we had an infinite amount of time to complete our boards,
this might be a good option, however this is not the case here.  Schedule
is our greatest obsticle.  So, we have reduced the size of our anti pad on
our vias and many of our few remaining through hole parts.  The amount of
reduction was arrived at through experimentation, though generally speaking
our anti padds are declared as being 30-40 mils over the FINISHED hole size.
And yes, that is really tight, but we are still able to drill our board
two up.

As example, our via is a 32 mil round pad with an 18 mil hole.  The anti
pad we use is 45 mils in diameter, this is 27 mils over the finished hole
size (13.5 mil annular ring).  -- we do not use a thermal tie on our vias.
For through hole component pads, we normally add 40 mils to the FINISHED
hole size to get the anti pad size.

Ok, now I've told you how we do it, now you tell me how you guys go about
solving this problem.  I'd warrent that punched up planes cause you folks
in the personal computer industry problems as well.  What is your via size,
drill and anti pad size?

Ken Barrett
[log in to unmask]
Cisco Systems
San Jose CA
408-526-5625

> From [log in to unmask] Tue Sep 17 13:24:02 1996
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> Ken Barrett
> 
> What is the basic size of the antis that you are using.  Is it something 
> like Drill Size  + .020 or Drill Size + .040.  What do you mean by reduce 
> anti size.
> 
> Max Thorson
> [log in to unmask]
> 713-514-7526
> -------------
> Original Text
> >From [log in to unmask], on 9/17/96 11:16 AM:
> We have been using vias without thermal pads for some time now, and have
> had no problem at all.  To my knowledge our fab vendors did not even notice
> the difference.  
> 
> Due to our heavy use of smt, virtually all our boards are 100% or 99.99%
> surface mount, removing the thermal pad and connecting our vias directly to
> the plane improved the emi-esd characteristics of our boards.  It has been
> a good deal all around.
> 
> In addition to this, we have also reduced the size of our anti pads.  We
> were having problems with signal quality due largely to "impedance bumps"
> which would occur when a trace passed a pad with a large anti pad.  This
> was because as the trace would pass over the anti pad, it would suddenly
> not have a ground layer to associate to.  To cure this problem, we have
> reduced our anti pads to a size where when traces pass by at minimum 
> distance,
> there is adaquate coverage by the associated layer.
> 
> my two cents worth...
> Ken Barrett
> Cisco Systems
> San Jose California
> ([log in to unmask])
> 
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