All,
The following is my attempt to compile responses to design questions I posted.

Question:     
Has anybody been using SMT Plus land patterns? They are advertising a lib. 
for P-Cad. How do they compare to the IPC 782 Patterns?

Comments:
1. Jim Blankenhorn (of SMT PLUS) once wrote an article commenting on the 
IPC-SM-782 document. It was common sense type notes concerning several of 
the footprint dimensions in 782 that were questionable. I'm sure he would send 
you a copy if you call him. Personally, I have never heard a complaint about 
anything in the SMT Plus library, and I tend to trust someone who gives 
solutions based on 1000's of real-world assemblies rather than the ones decided 
"by committee"

2.>Here at TRW we have implimented the SMT Plus footprints as our standard. When
>I first saw the pre-draft of 782A I about croaked. It's no longer a design
>standard, it's only a guide (as it implies) and MUST be tailored to your own
>practices (fab and assembly issues). We could use it as a standard before the
>Rev A as it wasn't a "left-field" all incompassing document.


3.The composition of the members the IPC-SM-782 committee include designers,
fabricators and assemblers. Their experiences come from thousands of real
life designs and assemblies. The main advantage to producing a standard in
this manner, is that they are all willing to share their experiences to
further better the industry. The IPC paper document is for sale, but the
technical information remains in the public domain. 

The IPC standards receive a technical review from sources located around the
globe. These sources are users and designers of a broad spectrum of products
and applications. Yes, a standard, by committee, represents some
concessions, but none that sacrifices quality, reliability, or cost. When I
look at an industry standard, I use the information as a guide for what the
majority of the industry can accomplish in a cost effective manner. I may
wish to taylor the information for my particular process, but at least I'll
know what the long term effects will be.


The comment heard most often, involving the original IPC-SM-782, was that it
was difficult to tailor to one's specific process. The users asked for a
standard that would provide sufficient information to apply the land pattern
principles to newly released components, as well as customize the land
pattern for their own processes. In addition, they questioned the fact that
we did not provide an input for machine accuracy or fabrication tolerances. 

When the committee drafted the 782A, they took these wishes into
consideration. The result is a standard that provides information on the
principles of land pattern creation, as well as what variables our peers
recommended to be used in the calculations.

As with the original 782, if one did not wish to make calculations, they
would simply use the values in the tables. If you were energetic and wished
to customize or create a new land pattern, then you had the formulas to work
with. The IPC supplemented the 782A with an electronic version. This
electronic spreadsheet simplifies the creation of new land patterns. One
would input the component size and tolerances, assembly accuracy,
fabrication tolerances, and desired solder fillet information. The land
pattern would be created with immediate feedback concerning your solder
fillet goals. The designer can then modify some of his numbers to achieve
fillet and/or land pattern goals. If the designer did not wish to create new
variables, he simply used the default values from the standard table.

I would hate for any standard to force anyone to be creative, let alone
prematurely croak. 


4. have 1 customer that uses the Ruppert Design Library created for SMT Plus 
(I beleive). It seemed to work OK. I use my own whenever I can.




Question:     
What are you doing as far as via's and conductors under SMD components? I 
noticed the P-Cad lib has keepouts under the chip components. I have been 
routing traces under SMD and have not had any problems.

Comments:
1 It has been quite awhile since I've even SEEN a PCAD library part (we make
our 
own) and am kinda surprised about built-in keepouts. Several recent articles 
mention having to customize glue dispensing over traces in high volume 
assemblies so it might be good to speak to the assembler about it. But look at 
other boards; almost every design you see has traces under chip devices! From 
my experience vias are okay if they are tented, otherwise the inability to 
clean properly may cause early failure (from corrosion). 

2Hasn't been a problem with us. 'Course we are not military, and that seems to
>be the only case I can think that requires this. It's mostly a concern for
>reliability, and whether the pcb is clean under the SMD.
> 

3 Putting vias and tracks under smt parts with no problem.

4.-I run vias (.030/.018) .005" from the connecting pad as a rule but have 
had some success running into the land. Traces work well also. (1 oz. Cu).

5.I don't place via's under chips SMD (0805 ... 7243) because it can create
shorts and makes it very difficult and assymbly houses however I have seen
via's for the same net on SMD pad (minimize the conductor from SMD pad to
via for high speed design).There is no problem running a trace between SMD
pad as long as keep the minimum space and may not do it if you have an
analog design.

6.We have not been putting vias under discrete comps. (i.e. chip caps,
resistors etc.)
You need to be careful when routing traces under components, you need to
allow more clearance to a smd resistor or cap because a trace could be exposed
depending on your soldermask opening.  also I had an occurence where a trace
routed close to a resistor smd pad caused interference.  I would recommend
at least 16 mils clearance minimum (my rule of thumb)
If you can avoid routing under discretes or between smd pads you should.
Always try to maximize clearances wherever possible.





Question:    
Has anyone needed to provide a glue dot file for mfg? I noticed that P-Cad 
has that capability but I have never had to provide one in the past. It was 
always created from the placement file.

>Glue dots are fine, provided it's what your assy house can use and will use.
>We don't provide it, because it's really too hard to stay abreast of what our
>many assy houses can and can't do, or can do faster with more data. But, that's
>not to say if you work with one assy house you couldn't provide them this.


Question:     
Silk Screen legend sizes seem to be very large on most commercial lib's 
compared to what I have been using. I seem to get away with .008 width and 
sometimes down to .060 height. What is your experience?
Comments:
> For the last three companies I've worked at, 60high/8wide was typical, and 
50high for tight placements. One consideration about the width is that 8 looks 
crisp, very legible, but for higher volume the screen can get clogged, which 
will start leaving gaps. 

>Remember, first and foremost, the design lib (like 782A) will first need to be
>tailored to suit your needs and requirements BEFORE you use them. .008s and 
>.060 hts have worked fine for us. As long as you keep in mind what line widths
>you use compared with heights you won't get anything you can't read.

I work for a company that makes consumer electronics.  Our preferred 
silk-screen size is 1.5 mm (0.060) high, 0.2 mm (0.008) width.
     
Silk Screen legend sizes seem to be very large on most commercial lib's 
compared to what I have been using. I seem to get away with .008 width and 
sometimes down to .060 height. What is your experience?
     
I go as low as 45 height 5 width in tight discrete areas. That's as low as I 
would go. Use 55 height 5 width for chips and 65 height 5 width for 
connectors.

 Silk Screen legend sizes seem to be very large on most commercial lib's
compared to what I have been using. I seem to get away with .008 width and
sometimes down to .060 height. What is your experience?

3. The maximum size silk I use is .060.I also go down to .035 even IPC said
minimum is .040.If you have room(which you don't) give them whatever they
want. It will eat up by via's and other pad during fabrication.

I've used .050 height, and .008 width minimum.  some places can print it
fine, some can't.  **



Question:     
I have just finished a Design for a client that demanded that all components 
be orientated in the same direction and also all of them lined up, nice and 
neat. Great idea if I would have had twice the board area to work with. I 
know the desirability of this but I also like to think form follows 
function. Many of the original reasons for doing this are obsolete. The 
board is finished now but I just know placing the parts for optimal routing 
would have resulted in much shorter runs, and a more functional layout. What 
is your opinion? How are you doing it?
     
Comments:
Having all the components line up nice and neatly on the PWB improves manual 
"inspectionability," and improves solderability using an IR reflow process.  
However, most contract assemblers are using convection reflow which reduces the 
shadowing effect.  The problem is just what you had encountered, 
non-optimization of trace routing.  If the engineer is developing a high-speed 
circuit, they just may be SOL.  Don't forget to point out to the engineer that 
layer-count could increase, which would increase the cost of his board (maybe 
unnecessarily).  This topic is not good to make generalizations.  It really 
comes down to the design at hand.

>Tough question, because I sometimes can't help going for beauty if I have the 
time, the artist in me I guess... but not if the circuit is degraded. 
I think you might benefit from asking more questions up front just to 
understand the issues your customer/company is considering. Maybe they want 
your board to grace the cover of their new brochure, eh? 

I can only respond to this one question.  From an EMI point of view, 
this can lead to disaster.  Lining everything up can destroy good to 
excellent circuit partitioning by introducing cross talk within the 
ground plane.  Depending upon the family of circuitry, this can range 
from bad to really bad.  

Routing parts in a line can also force you to develop loops from 
traces that in the near field spell disaster.

Both of these leave some scratching their heads.  Others begin the 
"adding more caps", "more gaskets", or "more ferrites" game to pass FCC.

Your point about shorter lead lengths is well taken.  Again, depending 
upon what family the circuit is from.

>TTL boards, this is desirable. For high-speed ECl/MECL boards this practice
>will go the wayside. Function will be more important. I don't personally care
>for "optimal" placement because it doesn't save me a dime with pick&place. What
>does is the type(s) of components you use (dip, SMT or dip/SMT) and placement
>design issues (have you considered all mfg requirements and practices?, spacing
>reqmts, fine pitch, fiducials, tooling holes, etc.)


As far as lining up the components and facing them all the same 
     direction:  Our manufacturer's pick-and-place machines can rotate 
     their heads only 90 degrees.  I am allowed to place my components in 
     only two directions (i.e.:  0 degrees and 90 degrees OR 180 degrees 
     and 270 degrees).  Any variation on this would require extra setup 
     time and some components may be put in backwards accidentally.  
     Perhaps if you talk to your customer, they will allow you to follow 
     this rule.  It may not be perfect, but it might help.

Great idea if I would have had twice the board area to work with. I
know the desirability of this but I also like to think form follows
function. Many of the original reasons for doing this are obsolete. The
board is finished now but I just know placing the parts for optimal routing
would have resulted in much shorter runs, and a more functional layout.

Unfortunately, sometimes a purchasing decision is made by "gee it looks so
pretty"... so I think the circuit functioning is top in priority, but it
should look
presentable if possible.
**




Question:
I also was prohibited from putting chip caps on the solder side, even though 
I routinely do it with other designs. Are any of you designing boards that 
are waved with chip caps on the solder side?

Comments:
In addition, you should not be prohibited from placing passive chip components 
on the secondary side of the PWA.  The person(s) requiring this may be concerned
about electrical testing of the PWB which would require simultaneous, 
double-sided testing because of the existence of SMTs on two sides.  As good 
design practice, you really should attempt to place all components on one side 
of the PWA.  There are many "hidden" costs when components are placed on two 
sides viz a viz one side.  However, you shouldn't be PROHIBITED.

The one issue that I haven't seen anyone f/b to you yet is
utilizing 1206 0.1 uF caps on the solder-side of a PWB that
will be processed using Wave-Flow soldering process.

We have had many failures in previous years with bottom
mounted .1/1206 caps, where they have been fracturing from
the heat cycling of the wave solder.  After extensive
cross-sectioning, and intense Vendor work, we found that the
massive layer count in a .1/1206 (& sometimes an 0805) was
the Culprit. Just too much packed into a small area.

These problems were solved by either reducing the values to
a .01 or a .047uF cap, or by duplicating caps where you
still needed the higher capacitance.

I know that we have since discovered that most vendors have
resolved these issues with their discretes, but we decided
it was much safer to design away from this value where
possible. This reduces the chance of a low quality vendor
being selected that may still have potentially poor part
integrity.

Currently it is undesirable to put .1uF smd caps on bottom side wave
due to cracking of the caps. Otherwise we are free to put smd caps on
the bottom.

>Sometimes what would benefit you as a designer could cost the company a lot in 
the long run. Even if you only want to put a few components on the back, it 
complicates the assembly drawing and may affect training field service manuals, 
parts may not be accessible after installation, Assemblers typically charge 
more automatically for double-sided boards and more steps are required, 
depending on the volume it might not be worth programming a pick-and-place 
machine for only a few parts on the backside which means those will have to be 
hand assembled; there are any number of reasons for making design decisions.
Again, you may want to start asking more questions...   


>Chip caps up to and including 1206 size are OK for wave side for our practices,
>and we don't put active comps on the wave side, BUT look at commercial boards.
>They do most anything. My practice is, if you use a good assy house, they will
>do your boards as best as they can to get you the best board possible. If they
>feel they can't achieve good solderability with wave on the back side, they
>will IR reflow or vapor phase both sides. Done.
>
>It's best to know what your fab and assy houses can and can't do for you, what
>input they need from you and how you can tailor that to your requirements.
>Enough said.

We put all discretes on bottom side and all chips on top. I think we wave on 
bottom side. I have also had really tight boards with chips and discretes on 
both sides, had no complaints. (may cost more to assemble however).
     

Putting caps on the bottom side (1206 pkgs and smaller) has not, to my
knowledge,
been a problem from an assembly standpoint - there were issues a while ago that
the caps were known to get stressed/cracks while being subject to solder
wave ops-
that appeared to manifest itself in later failures in the field.
Larger caps/tantalums (293a,b,c,d,e pkgs) should not be placed through
solderwave ops
due to their size/height and the possibility of cracking.


     
Regards
Fred Pescitelli
Phoenix Designs
1285 Turner Rd.
Lilburn, GA   30247
[log in to unmask]
770-923-3465

The mail list is run by SmartList v3.05
To unsubscribe from this list at any time, send a message to:
[log in to unmask] with <subject: unsubscribe> and no text.