This is the second of two related e-mailings.

WHAT'S IT ALL MEAN? & DISCUSSION

The IPC's-D-275 Table 3-1 electrical spacing is a 10% application requirement
of the specified dielectric strength requirements of the base material for 
conductive patterns layer-to-layer spacing (perpendicular) to the base 
material. That is, base material requirement 500 V/mil -vs- 50 V/mil (max PB
design). In effect, this gives the electrical/electronic design engineer a 
relatively low-risk, 10X safety factor/margin, for resonable reliability. In
contrast, the electrical spacing within a layer is not as robust. The
dielectric breakdown voltage base material requirement is about 50 V/mil and
the design standard varies from 10 to 50 V/mil, which at best is a 20%
application to no de-rating of the breakdown voltage. Therefore, the
electrical/electronic design engineer has an increased risk in product
reliability.

I will avoid making this response much tooooo long by avoiding the electrical
spacing concerns for surface conductive patterns and component leads other
that to say, becareful, analyze the requirements: and above all, do not use
solder resist for primary electrical insulation - especially for high voltage
(greater than 500 Vdc) applications.

MAJOR CONCERNS FOR HIGH VOLTAGE APPLICATIONS (based on industry
and personal
experiences)

The use of single-layer fabric core or prepreg's is a high risk choice. We've
had electrical shorts between power/ground planes with single-layer 106 and108
like fabrics in less than 1 hour with the application of 5 Vdc. The shorts
were very good, they checked out the current-limiting capability of the power
supplied at 70 A.

We've experienced failures (mostly hole-to-hole like the dielectric breakdown
test specimen) within the PB's base material along the fabric yarns due to
various combinations of high voltage, voids (non-wetting) in the yarns,
corona, and moisture absorption. Applications in the range of 5 - 60 kV

We've experienced plated-through hole (PTH) barrel to (internal) ground plane
shorts with "minimum" electrical spacing of100 micrometers (0.004 inch). The
assembly was being functionally tested in the engineering lab for about
3-weeks (turned off over weekends) to prove out the design. One weekend, the
PBA was left on, dentritic shorts were formed between the PTH barrel and the
ground plane because the PTH was an analog signal output network and remained
at about 10 Vdc when not in operation. The shorts were good for about 700 mA,
which was beyond the drive capability of the analog integrated circuit
component. Minimum electrical spacing and possibly marginal PB's and/or
assembly resulted in 0 (zero) reliability.

WHAT WE'VE DONE ON OCCASION

In some applications, mostly experimental, short product life, low hazard/low
risk, and never in an IPC Class 3 or a "serious high-rel" (when you need to do
the best); we use the following "rule-of-thumb" -- Dielectric
strength/breakdown 50 Vdc(or ac peak)/mil -and- surface spacing 10 kV/inch
(multiple or submultiple thereof).

THE BOTTOM LINE, IT DEPENDS ON THE APPLICATION, WHO'S GOING TO
BE RESPONSIBLE
FOR THE INCREASED RISK, AND KNOWN/UNKNOWN
REGULATORY/SAFETY REQUIREMENTS.

Ralph Hersey
Lawrence Livermore National Laboratory
Phn: 510.422.7430
FAX: 510.424.6886
e-mail: 



On Tue, 9 Apr 1996 [log in to unmask] wrote:

>      
>      Does anyone know of the origin/derivation of the charts in Figure 3-4 
>      of IPC-D-275?
> 
>