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1996

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From:
"Greg Bartlett" <[log in to unmask]>
Date:
20 Jun 1996 13:38:00 -0400
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                      RE>Re[5]: Soldermask Tented Vias             6/20/96

I would be very careful with this report, if I were you.  I was in DEC during the time that this work was done and was in a position to review it carefully.  While I strongly AGREE with the results of this work (that Bare Copper does not present an added reliability risk and can actually be more reliable) and that Battelle does a great job with Flowing Mix Gas tests, I disagree with how this test was applied.  They took a test environment/procedure that was originally designed to stress gold-plated connector mating surfaces and tried to run an SIR degradation test in it.  In my opinion, this "test" didn't really show anything conclusive.  

Greg Bartlett
Mercury Computer Systems
Chelmsford, MA
[log in to unmask] 
--------
     Mike - do you have a title, report number, etc that I could have our 
     info center chase down a copy of the Battelle Labs report for me?
     
     
     Dave Hillman
     Rockwell Collins
     [log in to unmask]
     


______________________________ Reply Separator _________________________________
Subject: RE: Re[3]: Soldermask Tented Vias
Author:  [log in to unmask] at ccmgw1
Date:    6/20/96 9:43 AM


     
I also have a copy of this report. It addresses metal migration of fine line 
circuits under bias on FR4 and Polyimide. Major questions were raised 
concering the use of polyimide PWBs. So, if you have FR4 substrates, bare 
copper via edges or bare copper untented vias are probably OK. If the solder 
mask covers the bare copper -- great. The level of residual ionic 
contamination is critical (according to the Batelle report) to the 
reliability of fine line circuits. We have a design with untented bare copper 
vias in the preproduction phase now.
     
Mike Pisansky
Unisys
[log in to unmask]
 ----------
From: TechNet-request
To: TechNet
Subject: Re[3]: Soldermask Tented Vias 
Date: Wednesday, June 19, 1996 5:23PM
     
     
Yes!!!
     
I have a copy of a report from Batelle Labs (study commisioned by DEC)that 
concludes tin/lead is more problematic than bare copper from a corrosion 
standpoint. If any one out there has any data to support the negative 
position on exposed copper, I'd love to see it posted here.
     
     
Dennis Mitchell
Zycon
[log in to unmask]
     
     
     
______________________________ Reply Separator 
_________________________________
Subject: Re[2]: Soldermask Tented Vias 
Author:  [log in to unmask] at corp
Date:    6/19/96 3:53 PM
     
     
     Rodger -
     
     I vote for your suggestion! If you look at an assembly with solder 
     mask closely, one will find that the sidewalls of many surface 
     features are bare copper. I think that the electronics industry in 
     general has quite a bit of exposed copper functioning in the field 
     with few problems. The exposed copper issues I have been working seems 
     to be a "culture" issue (military product primarily) - the standard 
     question has been "won't it corrode if the copper is exposed?. There 
     will be design and use environment specific cases where bare copper 
     will be a problem but overall there are gains to be realized. Using 
     bare copper would mean that the printed wiring board would see one 
     less thermal excursion (no HASL or Refuse operation) which can only be 
     a good thing from a reliability standpoint. Lee Parker of AT&T gave me 
     a paper on the corrosion of exposed copper in several environments 
     over a 30 year period - if I can find that paper I'll post it here on 
     TechNet. Well TechNet - anyone else in support of bare copper?
     
     
     Dave Hillman
     Rockwell Collins
     [log in to unmask]
     
     
     
______________________________ Reply Separator 
_________________________________
Subject: Re: Soldermask Tented Vias
Author:  [log in to unmask] at ccmgw1
Date:    6/19/96 10:05 AM
     
     
     I don't know much about your soldermask issue, but I would like to see 
     some discussion of the exposed copper issue.
     
     We have felt for a long time that any exposed copper was unacceptable 
     but with the industry switching over to OSP more and more, we have to 
     accept a limited amount of copper exposure (when SMT pads don't get 
     paste).  If you are making SMT-only boards which don't flow across a 
     wave solder then the amount of exposed copper goes up tremendously.  I 
     recently talked to people at a company which is very prominent in the 
     electronics industry and has been allowing a large amount of exposed 
     copper on their PCB assemblies (look inside your PC and see how much 
     exposed copper you can find).  They have done a significant amount of 
     temperature and life testing and have seen no problems due to exposed 
     copper.
     
     If this is true, isn't it time to stop worrying about exposed copper 
     and start making boards and assemblies cheaper?
     
     Regards,
     
     Roger Held
     Hitachi Computer Products (America), Inc.
     
     
______________________________ Reply Separator 
_________________________________
Subject: Soldermask Tented Vias
Author:  [log in to unmask] at Internet-HICAM-OK 
Date:    6/19/96 8:48 AM
     
     
     
Good Morning,
     
We usually require soldermask over bare copper and tented vias (less than 
.020").  This typically means that the soldermask is dry film.  If a tented 
via is not required and liquid soldermask is used, it appears that the 
soldermask is suspect to flake off near the via knee, leaving a small amount 
     
of exposed copper.
     
Is liquid solder mask over bare copper compliant with vias when the plating 
is eletroless nickel - immersion gold?
     
Does the plating type matter?
     
Is the suspect of exposed copper a non-issue?
     
Thank you in advance of any comments.
     
Kevin Thorson
Lockhead Martin
Eagan, Mn
     
     
     
     


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