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| From [log in to unmask] Wed Jan 17 13: |
28:35 1996 |
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I have a 3-board set of very dense VME-size digital boards that I am developing an
ATE program for. Boundary Scan is not an option for this generation of board,
perhaps next time. I have two questions:
1. In bed-of-nails testing, does forcing the output of a device to a known state by
driving the e-c junction affect the boards reliability?
2. Is there a bed-of-nails tester that that works strictly as a monitor; that does not
require each node to be stimulated individually?
Thanks for your help.
-------------------------------------
Mike Cutter
Research Engineer
SRI International
[log in to unmask]
(415)859-3974
Everything cometh to he who waiteth
So long as he who waiteth
Worketh like Hell
While he waiteth
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