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| From [log in to unmask] Tue Feb 27 09: |
16:48 1996 |
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<Pine.3.89.9602270949.B51040-0100000@ipc> |
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The values ARE conservative. There is a 15% derating factor on top of the
fact that the source for that table is something of an mystery.
The minimum spacing per volt is being tightened in the IPC-D-275 revision
document(s), although the new table needs to be approved by IPC membership.
Mike Buetow
Technical Staff
On Tue, 27 Feb 1996 [log in to unmask] wrote:
>
>
> I have a customer who has asked what is the required spacing on
> both innerlayers and outerlayers for 1500 VAC (~2100 VDC).
> Outerlayers have dryfilm soldermask covering them.
> I looked up IPC-D-275 and have referenced the data from table 3-1.
> This customer feels these values are extremely conservative and
> is curious if other designers are using that criteria rigidly?
>
>
> [log in to unmask]
>
>
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