 
| Received: |
by ipc.org (Smail3.1.28.1 #2)
id m0tpfyP-00008qC; Thu, 22 Feb 96 12:42 CST |
| Encoding: |
18 TEXT |
| Old-Return-Path: |
|
| Date: |
Thu, 22 Feb 96 13:36:00 PST |
| Precedence: |
list |
| Resent-From: |
|
| Message-ID: |
|
| X-Status: |
|
| Status: |
O |
| From [log in to unmask] Mon Feb 26 12: |
38:35 1996 |
| TO: |
|
| Return-Path: |
|
| Resent-Message-ID: |
<"lBjMn3.0.zCF.SaBBn"@ipc> |
| Subject: |
|
| From: |
|
| Resent-Sender: |
|
| X-Loop: |
|
| X-Mailer: |
Microsoft Mail V3.0 |
| X-Mailing-List: |
|
| Parts/Attachments: |
|
|
We are contemplating using OSP's but in doing so will leave exposed copper
on the final assembly. Specifically, the test points, fiducials and vias.
We have discussed printing solder paste on the test points and fiducials
but are not sure how it will affect test and the placement equipments vision
system.
What are the long term affects of leaving exposed copper in these areas?
Does anyone else leave exposed copper on the final assembly?
What affect will printing solder paste on test points and fiducials have on
placement and test?
How are assemblers dealing with this issue?
Any information would be greatly appreciated.
Karl Kaylor
Thomson Consumer Electronics
[log in to unmask]
|
|
|
