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Can you be more specific, I think everyone experiences an increased
defect rate at finer lines and spaces.  Can you tell us what type of 
resist you are using?  What is the surface prep prior to DF lamination?
Are you seeing alot of resist chips in your developer or etcher?
Are you catching the defect at AOI or Test?  Are you pattern plating or
panel plating? What type of stripper are you using?  Please answer 
these questions first, then maybe this forum can you give some help.

Regards,
Josh Moody
Merix Corp.

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