TECHNET Archives

1996

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Condense Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Mime-Version:
1.0
Content-Type:
text/plain; charset=US-ASCII
Old-Return-Path:
Date:
18 Sep 96 12:01:55 -0400
Precedence:
list
Resent-From:
Resent-Sender:
TechNet-request [log in to unmask]
Content-Transfer-Encoding:
7bit
Status:
O
X-Mailing-List:
<[log in to unmask]> archive/latest/6301
TO:
Return-Path:
<TechNet-request>
X-Status:
X-Loop:
Received:
by ipc.org (Smail3.1.28.1 #2) id m0v3P8D-0000QzC; Wed, 18 Sep 96 11:05 CDT
Resent-Message-ID:
<"EV6UF3.0.vL7.Ot1Go"@ipc>
Subject:
From:
Barry Darnell <[log in to unmask]>
Sender:
Message-Id:
X-Mailer:
<UGate 2.10>
From [log in to unmask] Wed Sep 18 11:
35:27 1996
Parts/Attachments:
text/plain (22 lines)

I have recently started using vias in SMT.  At this point, only in 
resistors and caps.  I need info about this, specifically if solder mask 
should cover these vias, or be opened up, on the bottom of the board.

Thanks for any help!
  
Barry Darnell
Ext. 231
[log in to unmask]
CD Electronics, Inc.
Printed Circuit Board Designer

***************************************************************************
* TechNet mail list is provided as a service by IPC using SmartList v3.05 *
***************************************************************************
* To unsubscribe from this list at any time, send a message to:           *
* [log in to unmask] with <subject: unsubscribe> and no text.        *
***************************************************************************



ATOM RSS1 RSS2