 
| Mime-Version: |
1.0 |
| Content-Type: |
Text/Plain |
| Old-Return-Path: |
|
| Date: |
16 Aug 96 10:13:10 |
| Precedence: |
list |
| Resent-From: |
|
| Resent-Sender: |
|
| X-Status: |
|
| Status: |
O |
| X-Mailing-List: |
|
| TO: |
|
| Return-Path: |
<TechNet-request> |
| Resent-Message-ID: |
<"xVFYp1.0.V-9.8Ct6o"@ipc> |
| Subject: |
|
| From: |
|
| Received: |
by ipc.org (Smail3.1.28.1 #2)
id m0utJzl-0000MeC; Wed, 21 Aug 96 15:35 CDT |
| X-Loop: |
|
| From [log in to unmask] Thu Aug 22 06: |
13:18 1996 |
| Message-Id: |
<9608211945.AA0133@augat> |
| Parts/Attachments: |
|
|
Does any one have good references on multi-layer pcb design optimisation to
reduce
micro switching noise pick-up
We are operating a micro (switching speed 2 MHz) on a PCB with 72 dB of gain
in the 5 to 1000 MHz range and need to keep the noise pick to less than -90 dBm
we currently
have achieved -75 dBm micro noise
***************************************************************************
* TechNet mail list is provided as a service by IPC using SmartList v3.05 *
***************************************************************************
* To unsubscribe from this list at any time, send a message to: *
* [log in to unmask] with <subject: unsubscribe> and no text. *
***************************************************************************
|
|
|
