Received: |
by ipc.org (Smail3.1.28.1 #2)
id m0tjZqq-0000AkC; Mon, 5 Feb 96 16:57 CST |
Encoding: |
11 TEXT |
Old-Return-Path: |
|
Date: |
Mon, 05 Feb 96 14:14:00 PST |
Precedence: |
list |
Resent-From: |
|
Resent-Sender: |
|
X-Status: |
|
Status: |
O |
X-Mailing-List: |
|
From [log in to unmask] Wed Feb 7 15: |
42:06 1996 |
TO: |
|
Return-Path: |
|
Resent-Message-ID: |
<"tzwXN3.0.R27.Vje5n"@ipc> |
Subject: |
|
From: |
|
X-Loop: |
|
X-Mailer: |
Microsoft Mail V3.0 |
Message-Id: |
<31168148@smtp> |
Parts/Attachments: |
|
|
Relating to one of the last posting on 'Non-Functional Pads'.
Are PCB designers and/or PCB fabricators specifying minimum drilled hole to
internal feature spacing?
Example: The space from a drilled hole to the nearest internal pad or trace
not on the same electrical net. I am not including the connection pad or
the non-functional pad that may be present on the same layer as the feature.
We currently currently try to keep this spacing above 10 mils.
|
|
|