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From [log in to unmask] Fri Jun 7 10: |
25:29 1996 |
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"Jeff Seeger" <simon.ipc.org!bort.mv.net!rapidcad!jseeger> |
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Roger Held wrote:
> The problem is that the evaluation board had a shear crack in the
> barrel of a 12mil small via hole after 100 cycles of thermal shock
There is a publication, IPC-TR-579, dated Sept 1988, "Round Robin
Reliability Evaluation of Small Diameter Plated Through Holes in
Printed Wiring Boards" (I typed it right! I typed it right!), that
presents a large amount of analysis data from a cross-section of
vendors on via failures vs size and board type for several thermal
excursion tests.
I'm not sure the results presented are all that current, but there
were themes that probably persist.
I'll apologize for being unable to do justice summarizing the results,
but it doesn't lead me to think that your soldermask is the problem.
In fact this doc (along with some TechNet discussions) led me to
conclude "It is better to allow tangency or breakout (with fillets)
then to reduce via hole size", at least for cases with excursions
beyond 0-100C/more than 100 cycles, or a where a broad pool of ven-
dors is desired.
Good luck,
Jeff Seeger Applied CAD Knowledge Inc
Chief Technical Officer Tyngsboro, MA 01879
[log in to unmask] 508 649 9800
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