Received: |
by ipc.org (Smail3.1.28.1 #2)
id m0uJ3jE-0000E7C; Mon, 13 May 96 14:56 CDT |
Content-Type: |
text/plain; charset="us-ascii" |
Old-Return-Path: |
|
Date: |
Mon, 13 May 1996 13:03:41 -0700 |
From [log in to unmask] Wed May 15 20: |
12:27 1996 |
Precedence: |
list |
Resent-From: |
|
Resent-Sender: |
|
MIME-Version: |
1.0 |
Status: |
O |
X-Mailing-List: |
|
TO: |
|
Return-Path: |
<TechNet-request> |
Resent-Message-ID: |
<"ff6hT2.0.PkA.dFvbn"@ipc> |
Subject: |
|
From: |
|
X-Status: |
|
X-Loop: |
|
Content-Transfer-Encoding: |
quoted-printable |
Message-ID: |
<01BB40CC.9C75EA20@JOHNP> |
Parts/Attachments: |
|
|
1. We use a 5mil clearance with manual registration techniques. We will take it down to 3mil if we are trying to increase the solder dam (web) width.
2. For high volume production purposes, we like to see 5-7mil dam (web) width.
3. Yes, it is common practice for us to modify customers solder mask designs to accomodate manufacturing requirements (tolerances) and IPC requirements.
----------
From: Thad McMillan[SMTP:[log in to unmask]]
Sent: Monday, May 13, 1996 8:49 AM
To: [log in to unmask]
Subject: FAB: Soldermask Clearance and Web Width requirements
Designing soldermask webs is always a pain in the neck, particularly
for fine pitch.
I'd like to conduct an informal survey, supplementing Doug's excellent
questions below regarding soldermask:
1. Using LPI type masks what is the minimum nominal clearance
(Copper to soldermask) that PCB fabricators need to prevent soldermask
from encroaching onto the copper? I've got answers in the past
ranging from 2 mils to 5 mils.
2. What is the minium nominal soldermask design web width that can
maintained in production? I.E. a minimum width that I can expect to
still have a soldermask web remaining after processing. I've got
answers here in the past also from 2 - 5 mils.
Need both answers from as many fabricators as possible.
I am looking for a number suitable for volume production (i.e. >10K
panels per month).
Does a table exist in any IPC design guidelines indicating these
geometries?
Is it typical practice for PCB fabricators to modify soldermask
artwork to get the necessary clearance?
Thanks,
[log in to unmask]
______________________________ Reply Separator _________________________________
Subject: FAB: Soldermask Webs.
Author: [log in to unmask] at Dell_UNIX
Date: 5/11/96 7:50 AM
-- [ From: Doug Jeffery * EMC.Ver #2.10P ] --
Friends,
We have seen many designs that have smaller webs between SMP's than they
have circuits. Imagin creating a .003" line in Soldermask yet the board
has .006" traces. We have found that any Soldermask web design that is
.005" of web by design is reproducable and can be placed reliably, but
below .005" the LPI masks do no hold on.
The key reason is undercut. The LPI between SMP's is thicker than
anywhere else on the board. This requires that the exposure be set up
to accomadate the thicker material, however overexposure can cause
other feature problems. After you have optimised the exposure you play
with the developing until you keep a good dam between pads, Bingo you
are leaving ink in the holes. So, you crank up the developer and get
that ink out of the holes....Catch 22...
AT .005" feature size (dams) you are able to optimize the process,
below .005" dams the undercut takes the foot of the LPI down to .003"
or .002" which makes the adhesion a problem, hense the peelers and
redoposit problems that you expressed.
?What is the answer for .020" pitch devices that require .014" pad
widths?
?what is the answer for .006" lands on .012" centers?
I don't know but certainly we have to get to one. We have tried double
coating, Unpigmented material, reduced pigmented material..No
significant result differences. We try to get customers to leave use
.009" min space between SMP's to keep a dam (2/5/2 by design. This
makes LPI exposing a tighter regitration than our outerlayer
requirements.
|
|
|