---------- Forwarded message ----------
Date: Thu, 29 Feb 1996 08:35:58 -0600
From: ROGER HELD <[log in to unmask]>
To: [log in to unmask]
Subject: Re: Soldermask over vias

     At Hitachi, we like to cover the vias with soldermask (it is our 
     preferred practice).  This helps prevent solder bridging and helps 
     seat the boards in the ICT fixture.  However, it also masks vias that 
     may be used as test points to increase ICT coverage.  This is probably 
     not a problem with a two layer board but we have had to strike a 
     balance (between covered or not covered or partially covered).
     
     Roger Held
     [log in to unmask]


______________________________ Reply Separator _________________________________
Subject: Soldermask over vias
Author:  [log in to unmask] at Internet-HICAM-OK
Date:    2/28/96 10:26 PM


We haave a captive double sided plated-thru-hole shop for in-house products.
 The finished raw boards before component insertion are Copper with Nickle
plating (not HALS) and selective solder mask.  For certain mechanical 
considerations with the interface of the PWBs to other non-conductive parts 
(plastic housings) of the finished products, we do not wish to have solder 
bumps on the back of the finished board at via interfaces after wave 
soldering that side (the actual electronics are on top).  Simple solder mask 
seems to prevent these bumps from being formed.  Is there an IPC 
recommenddaation about soldermasking over thru-hole vias?  The hole may or 
may not be closed by the mask.