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1996

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From [log in to unmask] Mon Aug 26 10:
42:56 1996
Subject:
From:
Barry Olney <[log in to unmask]>
Date:
Mon, 26 Aug 1996 09:30:15 +1100
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Hi Joe,

If you would like to calculate the impedance of a particular board 
stack-up check out our Interactive Impedance Calculation on the 
In-Circuit Design web site: http://www.icd.com.au

The main variation will be with the dielectric constant of FR4 wich 
may vary from 4.2 to 5.2 but you can specify an exact value to the 
board manufacturer it required.

The Impedance calculator is based on formulae from the IPC-D-317 and 
allows you to alter trace width, dielectric constant, Pre-preg 
thickness and Cu thickness in order to select the desired impedance.

Cheers,

Barry
___________________________________________________

Barry Olney		      http://www.icd.com.au
Managing Director			

In-Circuit Design Pty Ltd   	Ph: +61 3 9205 9595
VeriBest Solutions Centre	Fax:+61 3 9205 9410
Suite 211, Princess Tower	Mbl:+61 4 1117 0827
1 Princess Street,				
Kew, VIC 3101, Australia    Email:[log in to unmask]
___________________________________________________


Joe Zdybowicz wrote:
> 
> joe,
> 
> We work with EMI a little.  I hope these suggestions help.  If you
> would like more explanation please let me know.  If this information
> is already known, then I apologize.
> 
> 1. planes should be on layer n-1, that is on a 10 layer board
>    move the planes to layers 2, and 9.  This will shield the internal
>    layers 3 thru 8.
>       - If you have a dense board with lots of vias, you may also
>         consider using 2 oz copper for the planes.
>       - If the planes are currently next to each other on the internal
>         layer, the coupling or capacitance may be a concern.  Some board
>         manufacturers offer buried capacitance.  Please let me know
>         if you need an explanation or any other info.
> 
> 2. Get with your design engineer and discuss termination for ALL clock
>    signals.  No matter how short the trace is, Clocks are the biggest
>    source for radiation, and termination will help much.
>       - my suggestion for termination would be AC termination on a
>         trace which is daisy chained.  AC termination is a series
>         resistor, and cap to ground at the end of the trace, near the
>         last input pin.
> 
> 3. The termination makes a big difference in the radiation, but it is
>    also important to route the siganl on the internal layers as much as
>    possible.  Again this will take advantage of the planes acting as
>    shields.
> 
> 4. Also try designing with impedance in mind.  Though for most
>    frequencies simply specifying the dielectric thickness, and routing
>    with the proper trace width is enough.  All the board shops I know will
>    do an impedance calculation, and can provide you with a suggested
>    dielectric thickness and trace width.  The impedance should match the
>    input impedance of the receiver ICs.  I suggest you request the impedance
>    calculation from the board shop which will fab the board, you may find
>    the results change slightly from board shop to board shop. To the best of
>    my knowledge, the change in the answers to the impedance calculation are
>    due to variables in materials, prepreg selections, and etc from one shop
>    to the next.
>       - In this case, you may provide the trace width, and impandance to
>         the board shop, and ask for the dielectric thickness.
> 
> 5. Finally, adding a copper pour to your outer layers will also help to
>    shield EMI, but it is important that there is NO floating copper.
>    Make shure ALL your copper pour is connected to ground.
> 
> 6. Eliminate ALL 90 degree angles on traces, and planes.  All 90 degree
>    angles radiate, it is important to run your clean up utilities if you
>    haven't already.  Also consider the planes as capable of radiation
>    especially at higher frequecies, so 45 all the corners.
> 
> I do not know how much time you have to make changes, but please choose
> the suggestions which make the most sense for your circumstances.
> 
> joez
> -----------------------------------------------------------------
>  Joseph Zdybowicz                      FORE Systems
>  CAD Engineer                          174 Thorn Hill Road
>  Email:   [log in to unmask]                Warrendale, PA 15086-7586
>  Direct:  412-772-6552
> -----------------------------------------------------------------
> 
> >                                _\\|//_
> >                               (` O-O ')
> > +==========ooO-(_)-Ooo=============================+
> > Need help with EMI !
> >
> > EMI emissions problem !
> > What would be the best solution to reduce EMI on a ten layer board,
> > surface
> > mount components on both sides, 6 or 8 mil space/trace ?  Anyone with
> > experience in this area ?
> >
> > Telxon Corporation
> > Principle PC Designer
> > Joe Gee
> > Email: [log in to unmask]
> >
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