DESIGNERCOUNCIL Archives

1996

DesignerCouncil@IPC.ORG
Options: Use Monospaced Font
Show Text Part by Default
Condense Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Mime-Version:
1.0
Content-Type:
text/plain; charset=US-ASCII
Old-Return-Path:
<[log in to unmask]>
Date:
Wed, 26 Jun 96 6:10:41 EDT
Precedence:
list
Resent-From:
[log in to unmask]
Resent-Sender:
DesignerCouncil-request [log in to unmask]
X-Status:
Status:
O
X-Mailing-List:
<[log in to unmask]> archive/latest/1793
Content-Length:
827
TO:
<[log in to unmask]>
Return-Path:
<DesignerCouncil-request>
X-Loop:
[log in to unmask]
Resent-Message-ID:
<"FNPOk3.0.Xy8.LYHqn"@ipc>
Subject:
BGA Footprints
From:
"Gary S Thomas" <[log in to unmask]>
Received:
by ipc.org (Smail3.1.28.1 #2) id m0uYsLu-0000CiC; Wed, 26 Jun 96 06:01 CDT
From [log in to unmask] Wed Jun 26 13:
32:13 1996
X-Priority:
3 (Normal)
Message-Id:
<vines.ZUC9+,[log in to unmask]>
Parts/Attachments:
text/plain (21 lines) 
I have a project on the horizon that will use a 19 x 19, 50 mil pitch BGA 
(357 pins).  I have no experience with BGA's and could use some help on 
getting the traces out from the center of the pattern.  If I apply our std 
SMT pcb design rules and use a .012 via with a .028 pad, the real estate 
disappears in a hurry and I'll need 20 layers just getting out of the BGA.  
What are you doing?  Are you using a via hole smaller than .012, or crushing 
down the via pads much smaller than required for normal fab allowance?  Are 
you using a very small via hole in the BGA solder pad?  I know AT&T has been 
putting via holes in SMT footprints for years using (I think) a .007 hole. .. 
AT&T are you out there?                                            

Sure would appreciate any input.

Thanks

gary ..

Bailey Controls Co.

ATOM RSS1 RSS2