I notice that the previous responses that you received on your
problem with chip capacitor cracking have focused on the depaneling
operation.  While depaneling can induce flexure of the board which
will result in high bending stresses in the chip capacitors located
near the edge, have you identified a trend which points you in that
direction.  That is, are the capacitors that are cracking located
near the board edges?

If not, your problem may be more one of thermal stress.  The industry
had a severe multilayer chip capacitor cracking problem in the
late 1980's.  At our company we did a great deal of testing and 
crack analysis we found that there was a trend on capacitor dielectric
material, and supplier/construction of the capacitors.  NPO type
capacitors did not crack.

The load to the capacitor that was causing it to crack was a thermal
load caused by the temperature difference (delta T) between the
end of the preheat and the solder wave in the wave solder process
We have all but eliminated cracking problems by strick control of
suppliers, changing from a CDR04 case capacitor to a CDR32 or CDR33
case capacitor, and by controlling the wave solder process parameters
to limit the thermal shock  to the capacitor.  Depending on your
supplier, the recommended thermal shock is 80-100 deg F.  With the
CDR32 or CDR33 it can be as high as 120 deg F.

If you haven't solved your problem by looking at the previous 
suggestions, you may want to thermocouple your board and determine
what thermal shock these parts could be seeing.

Regards,

Peter H. Cote