Comments by: Randy Reed@Eng@ECB
Originally To: SMTP@FgF1s1@Servers[[log in to unmask]]
Original Date: Friday, December 1, 1995 at 10:45:10 am PST
Originally From: Randy Reed@Eng@ECB
Comments:
-------------------------[Original Message]--------------------------
Alain,
I agree with the other stated opinions that a smear removal or etchback process is strongly suggested for reliable interconnect. There are particular dangers to a three post lock or C-lock that were not discussed by the gentleman from Sandia Labs.
The 3 post lock puts significant stress on the end of the interconnect. When etchback was considered as the only alternative for a reliable interconnect (1960's and 70's) with Grade 1 copper internal copper layers, crack internal layers were rampant. The Defense Industry response was the conversion of the copper clad from Grade 1 to Grade 3 to reduce the likelihood of cracking. The conversion was a great success at reducing the crack layer defect but did not entirely eliminate it. The reason for the lack of total elimination was the stress that the 3 post lock etchback put on the internal layer.
A 3 post lock will give a reliable connection at the metallize line and transfer the high stress at the interconnect to the copper clad in the from of cracks. I have not seen a study to date that substantiates a crack layer is more reliable than an interplane separation.
The bottom line is a smear removal or etchback is required. I would not limit a board fabricator to 3 post lock etchback. The smear removal option is a reliable process when managed correctly. If the fabricator wants to change to the smear removal process, I would look at their process control measures, in-process audit plan for interplane separations, and the reliability data (thermal shock for 100 cycles) that the chosen alternate chemistry makes reliable interconnects.
Randy Reed
Merix Corporation
Jon Holmen <[log in to unmask]> Wrote:
|
|
| Alain,
|
| I talked to Floyd Gentry, current Chairman of the IPC-A-600
| and Arny
| Andrade who was the chairman of the A-600E. You can email
| Arny if you
| would like mor information on the tests performed by Sandia.
| His address
| is [log in to unmask] Their replies are as follows:
| -------------------------------------
|
| Multilayer boards without etchback exhibit higher electrical
| resistance during
| thermal shock and cycling. This has been substantiated by
| controlled
| environmental testing conducted here at Sandia National
| Laboratories on boards
| specifically designed for this purpose.
|
| It's not stated whether these boards are epoxy or
| polyimide construction.
| Polyimides which are typically used for high temperature
| applications can
| generally be fabricated with only a smear removal process due
| to their higher
| glass transition temperature (Tg) which results in less
| thermal expansion.
| However, drill smear can occur in any of these materials
| which must be removed
| before plating.
|
| Consequently, I would personally insist on at least a
| smear removal
| process at the very minimum.
|
| I would also question the validity of the 10-15% cost
| savings. If a smear
| removal is substituted for deep etchback, a shorter cycle
| might be possible
| and glass etch might be eliminated. However, I feel that a
| small reduction in
| cycle time would not justify a potential reduction in long
| term reliability.
|
| I would recommend that either a etchback or smear
| removal be continued
| depending upon the material construction and/or application
| requirements. I
| don't know of any reputable fabricator who couldn't
| accommodate one of these
| requirements in a cost effective manor.
|
| Floyd Gentry
| Sandia National Labs
| __________________________________________________
|
| Etchback enhances the innerlayer interconnects. One ounce
| inner layers measure
| approximately 1.1 to 1.3 mils in thickness but with 1-mil of
| etchback the
| contact area increases to 3.1 to 3.3 mils establishing a "c"
| type
| interconnect. Inner layer connections are stressed during
| assembly
| soldering operations and can result in interconnection cracks
| and/or opens but
| filled with solder. This connection can result in latent
| interconnection
| failure.
|
| Automotive environments are very severe and should be
| designed to high-rel
| requirements.
|
| Lab tests at Sandia verified the need of etchback. Test PWBs
| with both
| chemically cleaned and etchback interconnections were
| fabricated.
|
| Thermal cycles at 500F were performed using hot oil and IR as
| the heat medium.
| Resistance measurements were taken after each cycle.
|
| Results: Chemically cleaned interconnects increased
| resistance ending in open
| circuits. Etchback interconnects maintained their initial
| resistance.
| 40-cycles were performed with each heat medium with the same
| results.
|
| Therefore 10% to 15% savings may be false economy.
|
| Arny Andrade
| Sandia National Labs
|
|
| ****************************************************
| Jon Holmen
| Technical Project Manager
| IPC
| 2215 Sanders Road
| Northbrook IL 60062-6135
| Phone (708) 509-9700 ex329
| Fax (708) 509-9798
| e-mail [log in to unmask]
| *****************************************************
|
|
| On Tue, 21 Nov 1995, Fouquet, Alain wrote:
|
| >
| > To all,
| >
| > In an effort to reduce cost, our boards manufacturers are
| proposing to
| > remove the requirements for etchback. This is reported to
| be a saving of
| > 10-15% of the bare board. For an equipment subject to be
| used in an
| > environment which may be similar to a car and possibly
| marine types,
| > questions are:
| >
| > 1- Do we put ourselves in a position where reliability will
| drop
| > significantly if etchback is not specified?
| >
| > 2- Is etchback normally used in the automotive industry for
| multi-layer
| > board if used? If not what alternative to use?
| >
| > 3- Is the 10-15% cost reduction realistic?
| >
| > 4- General consumables like computers, are they using this
| process?
| >
| >
| > Any other comments would be appreciated.
| >
| >
| > Alain Fouquet
| > Canadian Marconi Company
| > Ville Saint-Laurent, QC, Canada
| > email: [log in to unmask]
| >
| >
|
|
