Bob:

Chip scale packages parallel standard SMT packages in form factor; both 
come in peripherally leaded and area array formats. Chip scale packages 
are designed to facilitate burn-in and test of the silicon chip prior to 
assembly, resulting in a solution for known good die. The packages are of 
minimal size (no more than 1.2X the area of the original die size) and 
are surface mountable as opposed to wire bonded.

You may want to obtain J-STD-012, Implementation on Flip Chip and Chip 
Scale Technology. It is a joint IPC-EIA standard, and should be available 
in the next few months.

Mike Buetow
IPC Technical Staff
7380 N. Lincoln Avenue
Lincolnwood, IL 60646
P: 708-677-2850, ext 335
F: 708-677-9570
[log in to unmask]

----------------------------------------------------------------
On Thu, 10 Aug 1995, Scicards(R) user id wrote:

> To whom---
> 
> I hate to clutter up the "EMPLOYMENT PAGE" with a need/interest of a technical
> nature, but can someone give me an overview (50 words or less) on chip scale
> devices and their attachement to the pwb. I think they are,simplistically,
> a coated chip with a ball grid attachement scheme. Further insight would be 
> appreciated. Much thanks in advance.
> 
>                                        Bob [log in to unmask]
> 
>