Bob-
     
     See also
     
     "Chip Scale Packaging," SMT Magazine, May 1995, pp.45-48, by Phil 
     Marcoux of ChipScale Inc., San Jose CA (408)955-9180
     
     "Development of the Slightly larger than IC carrier (SLICC)," Proc. 
     NEPCON West 1994, pp.1249-1256, Kingshuk Banerji of Motorola.  
     -Banerji's paper gives a good description of what is essentially a 
     type of CSP, comparing the package area ratio to other Moto processes, 
     including OMPAC, BGA, COB, DCA C4: all have a greater area ratio than 
     the SLICC (.060"pitch OMPAC/SLICC = 2.56/1.0).
     Banerji also discusses some reliability and board assembly issues.
     
     [log in to unmask]


______________________________ Reply Separator _________________________________
Subject: chip-scale attachement
Author:  [log in to unmask] at _internet
Date:    8/10/95 2:52 PM


To whom---
     
I hate to clutter up the "EMPLOYMENT PAGE" with a need/interest of a technical 
nature, but can someone give me an overview (50 words or less) on chip scale 
devices and their attachement to the pwb. I think they are,simplistically,
a coated chip with a ball grid attachement scheme. Further insight would be 
appreciated. Much thanks in advance.
     
                                       Bob [log in to unmask]