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Date: | Sat, 30 Dec 1995 07:37:20 -0600 (CST) |
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David,
The Surface Mount Council(SMC) coordinated a document on the subject that
you are interested in. It is in final type setting and will be printed
early in January, so it should be available by January 20th. The tile is:
J-STD-012 Implementation of Flip Chip and Chip Scale Technology
It is a roadmap on the issues related to the subject. It was developed by
IPC, EIA, JEDEC, MCNC, and Sematech. You can order a copy from IPC in
late January, however, I don't know the price as yet, since we are
getting printing costs at the moment. You can call our order department
closer to the date at 708 509-9700 ext 316 or 318.
It might interest you to know that there are twenty new standards
identified in J-STD-012, that need to be written to make the technology
main stream. We are starting work on the first six in January at the
Fiesta Inn in Tempe Arizona on (Jan 16 & 17). The first six identified are:
101 Semiconductor Design for Flip Chip/Chip Scale Applications
102 Mechanical Outlines for Flip Chip/Chip Scale Configurations
103 Performance Standard for Flip Chip/Chip Scale Bumps
104 Test Methods for for Flip Chip/Chip Scale Performance
107 Design Standard for Flip Chip/Chip Scale Mounting Structures
111 Design Standard for Flip Chip/Chip Scale Assembly Configurations
These are open meetings and any one can attend as we formulate the
strategy to complete these first six by the end of 1996. If you are
interested in participating let us know.
Dieter Bergman
On Thu, 28 Dec 1995, David Kennedy wrote:
> PCB Designers,
>
> I'm looking for general information about
> 'Chip Scale Packaging'. What types of components and
> their associated land patterns are available? Are any
> of you using this type of technology, and if so what types
> of concerns do you have in the manufacturing process?
> What type of challenges in the layout of the circuit, and
> any other general infromation?
>
> Thanks
>
> David Kennedy
> (516) 563-2400 ext 4856
>
>
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