Ken:

While I don't know if IPC 782A left out the wave spec on purpose or not, I 
do know that many manufacturers do NOT recommend the wave soldering of 
soic's. This is due to the preheat time and dwell time of the wave process. 
Many companies still use a tin/lead surface on the internal die carrier. 
During the wave process, the tin/lead carrier will reflow, resulting in 
dendritic growth and the possibility of internal pin shorting. Diamond/Supra 
found out about this the hard way, we placed smt resistor networks on the 
bottom side and waved them. The result was 80% field failures after about 1 
week. It seems that the parts tested ok, but with applied voltage over a 
period of time, the dendritic growth increased. The parts came from Dale, 
and the previous discussion is the results of their testing.

Currently, I have been able to implement an internal policy that only 
discrete parts may be placed on the bottom side for wave. If an active part 
or array must be placed on the bottom side, the assembly will have to be 
reflowed top and bottom. If two sided reflow is deemed to expensive, extra 
PCB real estate will have to be allowed to get all active components moved 
to the top.

If this is not helpful, or if you are in a situation forcing wave soldered 
smt ic's, send me an e-mail, I do have my old specs that I am willing to share.

>
>I've noticed that there is no spec for a different land pattern for
>bottom side, wave soldered soic's in my IPC-SM-782A spec.  Is my spec
>out of date, or have requirements changed such that I can use the top
>side, IR reflow geometry for a wave solder operation?  What about the
>theiving pads etc. etc. that we've installed in the past?  Are they
>still necessary?
>
>If information is missing in my spec, what equation should I use to
>generate a geometry that is not covered specifically by the '782A spec?
>
>Thanks in advance.
>Ken Barrett
>
>
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