We are interested in actual design rules for via-in-pad utilization:
    1) Should we modify existing pad size?  
    2) Where would you place the via (assuming 12 mil hole) in a soic
       pad: towards the edge of the pad or in the center.
    3) Would you limit (or rather balance) the number of holes on each
       side of a soic?   
    4) having a component on top side with vias-in-pads, should we  
       limit  the size of the pad on the bottom side?
    5) Should we cover, on bottom side, all via holes which connect to 
       smt pads on top side, with ssolder mask?  
    6) Isn't there a chance of "volcano effect" that will result in
       a void underneath the component terminal when going through
       the wave soldering?   
    7) Is it recommended to change to a harder (metal) squeegee? 

    Thanks in advance for any response

  Michael Weiner
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