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Subject:
From:
Wayne Thayer <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Wayne Thayer <[log in to unmask]>
Date:
Fri, 19 Jun 2020 11:42:54 -0700
Content-Type:
text/plain
Parts/Attachments:
text/plain (139 lines)
And then you get "cheaters" like me who sometimes allow a small hole to be
in a pad that we're mounting a component to. "Encroach" the soldermask on
the reverse side (hole diam + 100 microns for the mask opening) and put a
touch more paste on that pad, and voila: there's a via in the pad and it
works just fine. OR I demand via fill without cap. Yes, filling is a bit of
a PITA since you need to scrub off the residue anyway, and yes, the
customers of most fab houses are too dumb to realize that capping can come
with a price in reliability, but as long as you have plenty of area left
over for the solder joint, it works fine. And I'm talking actual fill here,
not that popular, unreliable, and disgusting process where people allow
soldermask to be cured in the vias.

Thought you guys might want some "opinion spice" with your Friday!

Wayne Thayer

On Fri, Jun 19, 2020 at 7:15 AM Dave Schaefer <[log in to unmask]> wrote:

> Via in pad can either be HDI, as in laser micro via, or conventionally
> drilled/filled/capped per IPC 4761 Type VII.
>
> HDI is typically dictated by very fine pitch BGA components where
> conventional vias will not fit and for very high density designs. External
> copper thickness is typically limited to 1/2oz maximum due to the laser
> drilling process.
>
> IPC 4761 Type VII can be used in high density designs with conventional
> vias. It enables placing vias in pad without causing manufacturability or
> quality problems. Unlike HDI, Type VII vias can be specified for designs
> requiring various copper thicknesses making it suitable for high current
> designs.
>
> Hth,
> Dave
>
> On Fri, Jun 19, 2020 at 12:00 AM TechNet automatic digest system <
> [log in to unmask]> wrote:
>
> > There are 3 messages totaling 93 lines in this issue.
> >
> > Topics of the day:
> >
> >   1. Via in Pad Terms and Definitions BGAs (3)
> >
> > ----------------------------------------------------------------------
> >
> > Date:    Thu, 18 Jun 2020 11:09:20 +0000
> > From:    [log in to unmask]
> > Subject: Via in Pad Terms and Definitions BGAs
> >
> > Fellow TechNetters:
> >
> >     I would like a clarification in the following Terms:
> >
> > Is Via In Pad, VIP, considered a micro via?    A typical microvia has a
> > capture land (where the via STARTS) and a smaller target land (where the
> > via ENDS.).
> > IPC-7095  5.1.3  Layering (Multilayers, Sequential or Build-Up)
> >
> > Victor,
> >
> > ------------------------------
> >
> > Date:    Thu, 18 Jun 2020 10:25:59 -0400
> > From:    Robert Kondner <[log in to unmask]>
> > Subject: Re: Via in Pad Terms and Definitions BGAs
> >
> > Victor,
> >
> > My 2 cents would be yes, a via in a pads is a micro via. And it is filled
> > and capped.
> >
> > Now if you have a really big pad ......
> >
> > Bob K.
> >
> > -----Original Message-----
> > From: TechNet <[log in to unmask]> On Behalf Of [log in to unmask]
> > Sent: Thursday, June 18, 2020 7:09 AM
> > To: [log in to unmask]
> > Subject: [TN] Via in Pad Terms and Definitions BGAs
> > Importance: High
> >
> > Fellow TechNetters:
> >
> >     I would like a clarification in the following Terms:
> >
> > Is Via In Pad, VIP, considered a micro via?    A typical microvia has a
> > capture land (where the via STARTS) and a smaller target land (where the
> > via
> > ENDS.).
> > IPC-7095  5.1.3  Layering (Multilayers, Sequential or Build-Up)
> >
> > Victor,
> >
> > ------------------------------
> >
> > Date:    Thu, 18 Jun 2020 07:30:54 -0700
> > From:    Morgan Viggers <[log in to unmask]>
> > Subject: Re: Via in Pad Terms and Definitions BGAs
> >
> > While almost every via has a pad, the term "via in pad" typically means
> > that
> > a via is present inside a SOLDER pad.  It can apply to a microvias, but
> is
> > not limited to them, can also apply to thru-vias.  From a PCB fab
> > standpoint, via-in-pads are typically filled and overplated to provide a
> > planar soldering surface.
> >
> > Morgan Viggers
> > Field Applications Engineer
> > ISU Petasys
> > 503.675.3877
> >
> > -----Original Message-----
> > From: [log in to unmask] [mailto:[log in to unmask]]
> > Sent: Thursday, June 18, 2020 4:09 AM
> > To: [log in to unmask]
> > Subject: [TN] Via in Pad Terms and Definitions BGAs
> >
> > Fellow TechNetters:
> >
> >     I would like a clarification in the following Terms:
> >
> > Is Via In Pad, VIP, considered a micro via?    A typical microvia has a
> > capture land (where the via STARTS) and a smaller target land (where the
> > via
> > ENDS.).
> > IPC-7095  5.1.3  Layering (Multilayers, Sequential or Build-Up)
> >
> > Victor,
> >
> > ------------------------------
> >
> > End of TechNet Digest - 17 Jun 2020 to 18 Jun 2020 (#2020-90)
> > *************************************************************
> >
>

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