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Subject:
From:
David Hillman <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, David Hillman <[log in to unmask]>
Date:
Wed, 26 Feb 2020 07:42:18 -0600
Content-Type:
text/plain
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text/plain (68 lines)
Hi TechNet - some BGA/CSP component fabricators do use sacrificial
solderballs on the corners of the components as detailed by Arnaud's
response. I don't know of any JEDEC specification that states a ratio
requirement.

Dave Hillman
Collins Aerospace
[log in to unmask]

On Mon, Feb 24, 2020 at 12:42 PM GRIVON Arnaud <
[log in to unmask]> wrote:

> Dear Victor,
>
> Trying to understand your actual need behind your somehow odd question...
> Would you be losing your balls one by one and trying to estimate how long
> you can last ?
> ;-)
>
> Or maybe just surprised by the high number of unused BGA bumps or balls
> for a given component?
> In my experience, some memory devices can be housed in large BGA packages
> with only à handful of balls actually used... In cases where the BGA ball
> matrix concentrates in the center of the   BGA and is far away from the
> edges, there may be some unused balls for mechanical support.
>
> Best regards,
>
> Arnaud Grivon
>
>
>
> Le 24 févr. 2020 18:33, "Stadem, Richard D" <[log in to unmask]> a
> écrit :
> I have never heard of a design guideline in the ratio of unused balls to
> circuit-connected balls. Not sure why there should be a ratio from an
> electrical performance standpoint?
> Solder balls that are not connected to the BGA circuity are used to
> balance out the package wetting forces during reflow, as well as to
> distribute CTE forces between the PWB and the BGA package. This is a BGA
> design characteristic, most likely any ratio would be in the component
> design guidelines in JEP95 or more specifically JEDEC Standard DR-4.14J.01.
> It may also be in some ANSI or other standard. Here is a link
> https://urldefense.proofpoint.com/v2/url?u=https-3A__www.jedec.org_standards-2Ddocuments_docs_dg-2D414h&d=DwIFAw&c=ilBQI1lupc9Y65XwNblLtw&r=qMshjwqeixvQjs1qYTl8aRebuaqi25nLzYlpmDF6tjI&m=XUw3vq2asPbRAB34dDQc4k9QFtSwMJuMtzSoTkY_oos&s=m07NgqnH9KyaPnw_CSQZvA5VaXe_bq4SrarvbyrDGqo&e=
>  This is a free download after registration.
>
> I don't have a copy, but somewhere in the JEDEC design standards for BGAs
> it should be listed, that is, if such a ratio actually exists.
> I wish I could be of more help, but that much I know.
>
> Odin
>
> -----Original Message-----
> From: TechNet <[log in to unmask]> On Behalf Of [log in to unmask]
> Sent: Monday, February 24, 2020 11:02 AM
> To: [log in to unmask]
> Subject: [TN] Sacrificial solder bump ratio in Nand gate BGA device
>
> Fellow TechNetters,
>
>    Is there an industry standard/guideline for the number of sacrificial
> solder bumps versus total solder bump count.   For instance, 64 sacrificial
> and 88 active bumps for a total of 152 bumps (42%)?
> In advance I thank you for your timely response in this matter.
>
> Victor,
>

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