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August 2019

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TechNet <[log in to unmask]>
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TechNet E-Mail Forum <[log in to unmask]>, Jack Olson <[log in to unmask]>
Date:
Wed, 28 Aug 2019 17:41:57 +0000
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TechNet E-Mail Forum <[log in to unmask]>, Dwight Mattix <[log in to unmask]>
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Subject:
Re: TYPE III vs TYPE V vias
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Dwight Mattix <[log in to unmask]>
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Re: but we need 100% assurance no solder will make a bump on the back side



100% epoxy fill. Most fabs will opt to do that VIPPO (Via In Pad Plated Over) these days -- though that's not necessary. Make sure if they do that the epoxy is a 100% solids type (e.g. San Ei).



-----Original Message-----

From: TechNet <[log in to unmask]> On Behalf Of Jack Olson

Sent: Wednesday, August 28, 2019 6:50 AM

To: [log in to unmask]

Subject: [EXT] Re: [TN] TYPE III vs TYPE V vias



On Tue, 27 Aug 2019 16:33:55 -0700, Stephen Pierce <[log in to unmask]> wrote:



>Area array pad over a plated via (blind or through) is the most common reason

>

>On Tue, Aug 27, 2019 at 3:49 PM Jack Olson <[log in to unmask]> wrote:

>>

>> When are caps on filled vias required by an application?



1) ours is a via array in single pad for thermal reasons, but we need 100% assurance no solder will make a bump on the back side

2) that's what I thought Dave was thinking about, too. just making sure I didn't misunderstand...

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